Datasheet > NDP7050

NDP7050

更新时间： 2024-11-20 22:40:35

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		晶体晶体管
页数	文件大小	规格书
12页	379K
描述
N-Channel Enhancement Mode Field Effect Transistor

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NDP7050 数据手册

March 1996

NDP7050 / NDB7050

N-Channel Enhancement Mode Field Effect Transistor

General Description

Features

75A, 50V. R_DS(ON)= 0.013W @ V_GS=10V.

These N-Channel enhancement mode power field effect

transistors are produced using Fairchild's proprietary, high

cell density, DMOS technology. This very high density

process is especially tailored to minimize on-state

resistance, provide superior switching performance, and

withstand high energy pulses in the avalanche and

commutation modes. These devices are particularly suited

for low voltage applications such as automotive, DC/DC

converters, PWM motor controls, and other battery powered

circuits where fast switching, low in-line power loss, and

resistance to transients are needed.

Critical DC electrical parameters specified at elevated

temperature.

Rugged internal source-drain diode can eliminate the need

for an external Zener diode transient suppressor.

175°C maximum junction temperature rating.

High density cell design for extremely low R_DS(ON)

TO-220 and TO-263 (D²PAK) package for both through

hole and surface mount applications.

_______________________________________________________________________________

Absolute Maximum Ratings T_C= 25°C unless otherwise noted

Symbol

Parameter

NDP7050

NDB7050

Units

V_DSS

Drain-Source Voltage

V_DGR

Drain-Gate Voltage (R_GS< 1 MW)

Gate-Source Voltage - Continuous

- Nonrepetitive (t_P< 50 µs)

V_GSS

± 20

± 40

I_D

Drain Current - Continuous

- Pulsed

225

P_D

Maximum Power Dissipation @ T_C= 25°C

Derate above 25°C

150

W/°C

°C

T_J,T_STG

T_L

Operating and Storage Temperature Range

-65 to 175

275

Maximum lead temperature for soldering

purposes, 1/8" from case for 5 seconds

°C

NDP7050.SAM Rev. D

12 3 4 5 6 7...12

中文翻译

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