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NDP4050 PDF预览

NDP4050

更新时间: 2024-11-07 22:29:07
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 晶体晶体管功率场效应晶体管开关脉冲局域网
页数 文件大小 规格书
6页 69K
描述
N-Channel Enhancement Mode Field Effect Transistor

NDP4050 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TO-220AB包装说明:TO-220, 3 PIN
针数:3Reach Compliance Code:unknown
ECCN代码:EAR99风险等级:5.74
Is Samacsys:N雪崩能效等级(Eas):40 mJ
配置:SINGLE WITH BUILT-IN DIODE最小漏源击穿电压:50 V
最大漏极电流 (Abs) (ID):15 A最大漏极电流 (ID):15 A
最大漏源导通电阻:0.1 ΩFET 技术:METAL-OXIDE SEMICONDUCTOR
JEDEC-95代码:TO-220ABJESD-30 代码:R-PSFM-T3
JESD-609代码:e0元件数量:1
端子数量:3工作模式:ENHANCEMENT MODE
最高工作温度:175 °C封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:FLANGE MOUNT
峰值回流温度(摄氏度):NOT SPECIFIED极性/信道类型:N-CHANNEL
最大功率耗散 (Abs):50 W最大脉冲漏极电流 (IDM):45 A
认证状态:Not Qualified子类别:FET General Purpose Power
表面贴装:NO端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子位置:SINGLE
处于峰值回流温度下的最长时间:NOT SPECIFIED晶体管应用:SWITCHING
晶体管元件材料:SILICONBase Number Matches:1

NDP4050 数据手册

 浏览型号NDP4050的Datasheet PDF文件第2页浏览型号NDP4050的Datasheet PDF文件第3页浏览型号NDP4050的Datasheet PDF文件第4页浏览型号NDP4050的Datasheet PDF文件第5页浏览型号NDP4050的Datasheet PDF文件第6页 
July 1996  
NDP4050 / NDB4050  
N-Channel Enhancement Mode Field Effect Transistor  
General Description  
Features  
These N-Channel enhancement mode power field effect  
transistors are produced using Fairchild's proprietary,  
high cell density, DMOS technology. This very high  
density process has been especially tailored to minimize  
on-state resistance, provide superior switching  
performance, and withstand high energy pulses in the  
avalanche and commutation modes. These devices are  
particularly suited for low voltage applications such as  
automotive, DC/DC converters, PWM motor controls, and  
other battery powered circuits where fast switching, low  
in-line power loss, and resistance to transients are  
needed.  
15A, 50V. RDS(ON) = 0.10W @ VGS=10V.  
Critical DC electrical parameters specified at elevated  
temperature.  
Rugged internal source-drain diode can eliminate the need  
for an external Zener diode transient suppressor.  
175°C maximum junction temperature rating.  
High density cell design for extremely low RDS(ON)  
.
TO-220 and TO-263 (D2PAK) package for both through hole  
and surface mount applications.  
____________________________________________________________________________________________  
D
G
S
Absolute Maximum Ratings  
Symbol Parameter  
TC = 25°C unless otherwise noted  
NDP4050  
NDB4050  
Units  
V
VDSS  
VDGR  
Drain-Source Voltage  
50  
50  
V
Drain-Gate Voltage (RGS < 1 MW)  
Gate-Source Voltage - Continuous  
± 20  
± 40  
V
VGSS  
- Nonrepetitive (tP < 50 µs)  
Drain Current - Continuous  
ID  
± 15  
A
- Pulsed  
± 45  
PD  
Total Power Dissipation  
50  
W
W/°C  
°C  
Derate above 25°C  
0.33  
TJ,TSTG  
TL  
Operating and Storage Temperature Range  
-65 to 175  
275  
Maximum lead temperature for soldering purposes,  
1/8" from case for 5 seconds  
°C  
NDP4050 Rev. B  
© 1997 Fairchild Semiconductor Corporation  

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