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NC7WP00L8X PDF预览

NC7WP00L8X

更新时间: 2024-02-09 22:04:12
品牌 Logo 应用领域
安森美 - ONSEMI PC逻辑集成电路触发器
页数 文件大小 规格书
9页 529K
描述
TinyLogic ULP 双通道双输入 NAND 门

NC7WP00L8X 技术参数

是否无铅: 不含铅生命周期:Active
包装说明:VSON, LCC8,.06SQ,20Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:1.41
系列:PJESD-30 代码:S-XDSO-N8
JESD-609代码:e4长度:1.6 mm
负载电容(CL):30 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.0005 A湿度敏感等级:1
功能数量:2输入次数:2
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:VSON封装等效代码:LCC8,.06SQ,20
封装形状:SQUARE封装形式:SMALL OUTLINE, VERY THIN PROFILE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.2/3.3 VProp。Delay @ Nom-Sup:43 ns
传播延迟(tpd):43 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:0.55 mm
子类别:Gates最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):0.9 V标称供电电压 (Vsup):1.2 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:1.6 mmBase Number Matches:1

NC7WP00L8X 数据手册

 浏览型号NC7WP00L8X的Datasheet PDF文件第2页浏览型号NC7WP00L8X的Datasheet PDF文件第3页浏览型号NC7WP00L8X的Datasheet PDF文件第4页浏览型号NC7WP00L8X的Datasheet PDF文件第5页浏览型号NC7WP00L8X的Datasheet PDF文件第6页浏览型号NC7WP00L8X的Datasheet PDF文件第7页 
TinyLogic ULP-A Dual  
2-Input NAND Gate  
NC7WP00  
The NC7WP00 is a dual 2input NAND gate in tiny footprint  
=
packages. The device is designed to operate for V  
0.9 V to 3.6 V.  
CC  
www.onsemi.com  
MARKING  
Features  
Designed for 0.9 V to 3.6 V V Operation  
CC  
2.1 ns t at 3.3 V (Typ)  
PD  
DIAGRAMS  
Inputs/Outputs OverVoltage Tolerant up to 3.6 V  
I  
Supports Partial Power Down Protection  
Source/Sink 2.6 mA at 3.3 V  
OFF  
CCKK  
XYZ  
Available in US8 and MicroPakPackages  
These Devices are PbFree, Halogen Free/BFR Free and are RoHS  
Compliant  
XXXX  
ALYW  
A1 B1 Y2  
7
6
5
A1  
B1  
1
2
3
4
8 V  
CC  
V
CC  
8
7 Y1  
6 B2  
5 A2  
GND  
4
CC, XXXX = Specific Device Code  
Y2  
KK  
XY  
Z
= 2Digit Lot Run Traceability Code  
= 2Digit Date Code Format  
= Assembly Plant Code  
= Assembly Site  
GND  
1
2
3
A
Y1 B2  
UQFN8  
A2  
L
= Wafer Lot Number  
US8  
YW  
= Assembly Start Week  
Figure 1. Pinout Diagrams (Top Views)  
ORDERING INFORMATION  
See detailed ordering, marking and shipping information on  
page 6 of this data sheet.  
A1  
&
&
Y1  
Y2  
B1  
A2  
B2  
Figure 2. Logic Symbol  
PIN ASSIGNMENT  
FUNCTION TABLE (Y = AB)  
Pin  
1
US8  
UQFN8  
Inputs  
Output  
A1  
B1  
Y1  
B2  
A
L
B
L
Y
H
H
H
L
2
3
Y2  
A2  
L
H
L
4
GND  
A2  
GND  
Y2  
H
H
5
H
6
B2  
B1  
NOTE: H = HIGH Logic Level  
L = LOW Logic Level  
7
Y1  
A1  
8
V
CC  
V
CC  
Publication Order Number:  
© Semiconductor Components Industries, LLC, 2005  
1
NC7WP00/D  
February, 2021 Rev. 1  

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