是否Rohs认证: | 符合 | 生命周期: | Obsolete |
零件包装代码: | SOIC | 包装说明: | VSON, |
针数: | 6 | Reach Compliance Code: | compliant |
HTS代码: | 8542.39.00.01 | 风险等级: | 5.84 |
系列: | P | JESD-30 代码: | R-XDSO-N6 |
长度: | 1.45 mm | 逻辑集成电路类型: | INVERTER |
功能数量: | 2 | 输入次数: | 1 |
端子数量: | 6 | 最高工作温度: | 85 °C |
最低工作温度: | -40 °C | 封装主体材料: | UNSPECIFIED |
封装代码: | VSON | 封装形状: | RECTANGULAR |
封装形式: | SMALL OUTLINE, VERY THIN PROFILE | 传播延迟(tpd): | 46.3 ns |
认证状态: | Not Qualified | 座面最大高度: | 0.55 mm |
最大供电电压 (Vsup): | 3.6 V | 最小供电电压 (Vsup): | 0.9 V |
标称供电电压 (Vsup): | 1.2 V | 表面贴装: | YES |
技术: | CMOS | 温度等级: | INDUSTRIAL |
端子形式: | NO LEAD | 端子节距: | 0.5 mm |
端子位置: | DUAL | 宽度: | 1 mm |
Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
NC7WP04P6X | FAIRCHILD |
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TinyLogic ULP Dual Inverter | |
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TinyLogic-R ULP Dual Buffer (Open Drain Output) (Preliminary) | |
NC7WP07L6X | FAIRCHILD |
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TinyLogic-R ULP Dual Buffer (Open Drain Output) (Preliminary) | |
NC7WP07P6X | FAIRCHILD |
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TinyLogic-R ULP Dual Buffer (Open Drain Output) (Preliminary) | |
NC7WP08 | FAIRCHILD |
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TinyLogic ULP Dual 2-Input AND Gate | |
NC7WP08_05 | FAIRCHILD |
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TinyLogic ULP Dual 2-Input AND Gate | |
NC7WP08K8X | FAIRCHILD |
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TinyLogic ULP Dual 2-Input AND Gate | |
NC7WP08K8X | ONSEMI |
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TinyLogic ULP 双 2 输入 AND 门极 | |
NC7WP08K8X_NL | FAIRCHILD |
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AND Gate, P Series, 2-Func, 2-Input, CMOS, PDSO8, 3.10 MM, MO-187CA, US-8 | |
NC7WP08L8X | FAIRCHILD |
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TinyLogic ULP Dual 2-Input AND Gate |