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NC7WP08K8X PDF预览

NC7WP08K8X

更新时间: 2024-01-07 06:21:45
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
9页 514K
描述
TinyLogic ULP 双 2 输入 AND 门极

NC7WP08K8X 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:VSSOP,针数:8
Reach Compliance Code:unknown风险等级:5.74
Is Samacsys:N系列:P
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:2.3 mm逻辑集成电路类型:AND GATE
湿度敏感等级:1功能数量:2
输入次数:2端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:VSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260传播延迟(tpd):46.3 ns
认证状态:COMMERCIAL座面最大高度:0.9 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):0.9 V
标称供电电压 (Vsup):1.2 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:2 mm
Base Number Matches:1

NC7WP08K8X 数据手册

 浏览型号NC7WP08K8X的Datasheet PDF文件第2页浏览型号NC7WP08K8X的Datasheet PDF文件第3页浏览型号NC7WP08K8X的Datasheet PDF文件第4页浏览型号NC7WP08K8X的Datasheet PDF文件第5页浏览型号NC7WP08K8X的Datasheet PDF文件第6页浏览型号NC7WP08K8X的Datasheet PDF文件第7页 
DATA SHEET  
www.onsemi.com  
TinyLogic ULP-A Dual  
2-Input AND Gate  
MARKING  
DIAGRAMS  
NC7WP08  
The NC7WP08 is a dual 2input AND gate in tiny footprint  
CCKK  
XYZ  
=
packages. The device is designed to operate for V  
0.9 V to 3.6 V.  
CC  
Features  
Designed for 0.9 V to 3.6 V V Operation  
CC  
2.2 ns t at 3.3 V (Typ)  
PD  
XXXX  
ALYW  
Inputs/Outputs OverVoltage Tolerant up to 3.6 V  
I  
Supports Partial Power Down Protection  
Source/Sink 2.6 mA at 3.3 V  
OFF  
Available in US8 and MicroPakPackages  
CC, XXXX = Specific Device Code  
KK  
XY  
Z
= 2Digit Lot Run Traceability Code  
= 2Digit Date Code Format  
= Assembly Plant Code  
= Assembly Site  
These Devices are PbFree, Halogen Free/BFR Free and are RoHS  
Compliant  
A
A1 B1 Y2  
L
= Wafer Lot Number  
A
1
1
8
V
CC  
5
7
6
YW  
= Assembly Start Week  
B
1
Y
2
2
3
7
6
Y
1
B
2
V
CC  
8
GND  
4
ORDERING INFORMATION  
See detailed ordering, marking and shipping information on  
page 6 of this data sheet.  
GND  
4
5
A
2
1
2
3
A2  
Y1 B2  
UQFN8  
US8  
Figure 1. Pinout Diagrams (Top Views)  
A1  
B1  
&
&
Y1  
Y2  
A2  
B2  
Figure 2. Logic Symbol  
PIN ASSIGNMENT  
FUNCTION TABLE  
Pin  
1
US8  
UQFN8  
Inputs  
Output  
A1  
B1  
Y1  
B2  
A
L
B
L
Y
L
2
3
Y2  
A2  
L
H
L
L
4
GND  
A2  
GND  
Y2  
H
H
L
5
H
H
NOTE: H = HIGH Logic Level  
L = LOW Logic Level  
6
B2  
B1  
7
Y1  
A1  
8
V
CC  
V
CC  
Publication Order Number:  
© Semiconductor Components Industries, LLC, 2005  
1
NC7WP08/D  
October, 2021 Rev. 1  

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