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NC7WP00K8X PDF预览

NC7WP00K8X

更新时间: 2024-11-20 11:12:51
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
9页 529K
描述
TinyLogic ULP 双通道双输入 NAND 门

NC7WP00K8X 数据手册

 浏览型号NC7WP00K8X的Datasheet PDF文件第2页浏览型号NC7WP00K8X的Datasheet PDF文件第3页浏览型号NC7WP00K8X的Datasheet PDF文件第4页浏览型号NC7WP00K8X的Datasheet PDF文件第5页浏览型号NC7WP00K8X的Datasheet PDF文件第6页浏览型号NC7WP00K8X的Datasheet PDF文件第7页 
TinyLogic ULP-A Dual  
2-Input NAND Gate  
NC7WP00  
The NC7WP00 is a dual 2input NAND gate in tiny footprint  
=
packages. The device is designed to operate for V  
0.9 V to 3.6 V.  
CC  
www.onsemi.com  
MARKING  
Features  
Designed for 0.9 V to 3.6 V V Operation  
CC  
2.1 ns t at 3.3 V (Typ)  
PD  
DIAGRAMS  
Inputs/Outputs OverVoltage Tolerant up to 3.6 V  
I  
Supports Partial Power Down Protection  
Source/Sink 2.6 mA at 3.3 V  
OFF  
CCKK  
XYZ  
Available in US8 and MicroPakPackages  
These Devices are PbFree, Halogen Free/BFR Free and are RoHS  
Compliant  
XXXX  
ALYW  
A1 B1 Y2  
7
6
5
A1  
B1  
1
2
3
4
8 V  
CC  
V
CC  
8
7 Y1  
6 B2  
5 A2  
GND  
4
CC, XXXX = Specific Device Code  
Y2  
KK  
XY  
Z
= 2Digit Lot Run Traceability Code  
= 2Digit Date Code Format  
= Assembly Plant Code  
= Assembly Site  
GND  
1
2
3
A
Y1 B2  
UQFN8  
A2  
L
= Wafer Lot Number  
US8  
YW  
= Assembly Start Week  
Figure 1. Pinout Diagrams (Top Views)  
ORDERING INFORMATION  
See detailed ordering, marking and shipping information on  
page 6 of this data sheet.  
A1  
&
&
Y1  
Y2  
B1  
A2  
B2  
Figure 2. Logic Symbol  
PIN ASSIGNMENT  
FUNCTION TABLE (Y = AB)  
Pin  
1
US8  
UQFN8  
Inputs  
Output  
A1  
B1  
Y1  
B2  
A
L
B
L
Y
H
H
H
L
2
3
Y2  
A2  
L
H
L
4
GND  
A2  
GND  
Y2  
H
H
5
H
6
B2  
B1  
NOTE: H = HIGH Logic Level  
L = LOW Logic Level  
7
Y1  
A1  
8
V
CC  
V
CC  
Publication Order Number:  
© Semiconductor Components Industries, LLC, 2005  
1
NC7WP00/D  
February, 2021 Rev. 1  

NC7WP00K8X 替代型号

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