Datasheet > NB2308AI4

NB2308AI4

更新时间： 2024-11-21 01:04:23

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
12页	195K
描述
3.3 V Zero Delay Clock Buffer

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NB2308AI4 数据手册

NB2308A

3.3 V Zero Delay

Clock Buffer

The NB2308A is a versatile, 3.3 V zero delay buffer designed to

distribute high--speed clocks. It is available in a 16 pin package. The

part has an on--chip PLL which locks to an input clock presented on

the REF pin. The PLL feedback is required to be driven to FBK pin,

and can be obtained from one of the outputs. The input--to--output

propagation delay is guaranteed to be less than 250 ps, and the

output--to--output skew is guaranteed to be less than 200 ps.

The NB2308A has two banks of four outputs each, which can be

controlled by the select inputs as shown in the Select Input Decoding

Table. If all the output clocks are not required, Bank B can be

three--stated. The select input also allows the input clock to be directly

applied to the outputs for chip and system testing purposes.

Multiple NB2308A devices can accept the same input clock and

distribute it. In this case the skew between the outputs of the two

devices is guaranteed to be less than 700 ps.

http://onsemi.com

MARKING

DIAGRAMS*

XXXXXXXXXG

AWLYWW

SOIC--16

D SUFFIX

CASE 751B

The NB2308A is available in five different configurations (Refer to

NB2308A Configurations Table). The NB2308AI1 is the base part,

where the output frequencies equal the reference if there is no counter

in the feedback path. The NB2308AI1H is the high--drive version of

the --1 and the rise and fall times on this device are much faster.

The NB2308AI2 allows the user to obtain 2X and 1X frequencies on

each output bank. The exact configuration and output frequencies

depends on which output drives the feedback pin. The NB2308AI3

allows the user to obtain 4X and 2X frequencies on the outputs.

The NB2308AI4 enables the user to obtain 2X clocks on all outputs.

Thus, the part is extremely versatile, and can be used in a variety of

applications.

XXXX

ALYWG

TSSOP--16

DT SUFFIX

CASE 948F

XXXX = Device Code

= Assembly Location

WL, L = Wafer Lot

= Year

The NB2308AI5H is a high--drive version with REF/2 on both

banks.

WW, W = Work Week

G or G = Pb--Free Package

(Note: Microdot may be in either location)

Features

 Zero Input -- Output Propagation Delay, Adjustable by Capacitive

Load on FBK Input

*For additional marking information, refer to

Application Note AND8002/D.

 Multiple Configurations -- Refer to NB2308A Configurations Table

 Input Frequency Range: 15 MHz to 133 MHz

 Multiple Low--Skew Outputs

ORDERING INFORMATION

Seedetailedorderingandshippinginformationinthepackage

dimensions section on page 9 of this data sheet.

 Output--Output Skew Less than 200 ps

 Device--Device Skew Less than 700 ps

 Two banks of four outputs, three--stateable by two select inputs

 Less than 200 ps Cycle--to--Cycle Jitter

 Available in 16--pin SOIC and TSSOP Packages

 3.3 V Operation

 Guaranteed Across Commercial and Industrial Temperature Ranges

 Advanced 0.35 m CMOS Technology

 These are Pb--Free Devices



Semiconductor Components Industries, LLC, 2010

Publication Order Number:

October, 2010 -- Rev. 8

NB2308A/D

12 3 4 5 6 7...12

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与NB2308AI4相关器件

型号	品牌	获取价格	描述	数据表
NB2308AI4DG	ONSEMI	获取价格	3.3 V Zero Delay Clock Buffer
NB2308AI4DR2G	ROCHESTER	获取价格	2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16, LEAD
NB2308AI4DR2G	ONSEMI	获取价格	3.3 V Zero Delay Clock Buffer
NB2308AI4DTG	ONSEMI	获取价格	3.3 V Zero Delay Clock Buffer
NB2308AI4DTR2G	ONSEMI	获取价格	3.3 V Zero Delay Clock Buffer
NB2308AI5H	ONSEMI	获取价格	3.3 V Zero Delay Clock Buffer
NB2308AI5HDG	ONSEMI	获取价格	3.3 V Zero Delay Clock Buffer
NB2308AI5HDR2G	ONSEMI	获取价格	3.3 V Zero Delay Clock Buffer
NB2308AI5HDR2G	ROCHESTER	获取价格	2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16, LEAD
NB2308AI5HDTG	ONSEMI	获取价格	3.3 V Zero Delay Clock Buffer

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