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NB2305AI1HDR2G PDF预览

NB2305AI1HDR2G

更新时间: 2024-11-24 03:03:31
品牌 Logo 应用领域
安森美 - ONSEMI 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 134K
描述
3.3 V Zero Delay Clock Buffer

NB2305AI1HDR2G 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:0.150 INCH, LEAD FREE, SOIC-8针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:1.47
Is Samacsys:N系列:2305
输入调节:STANDARDJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.9 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.012 A
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:8
实输出次数:4最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.25 ns
座面最大高度:1.75 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:3.9 mm
最小 fmax:133.33 MHzBase Number Matches:1

NB2305AI1HDR2G 数据手册

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NB2305A  
3.3 V Zero Delay  
Clock Buffer  
The NB2305A is a versatile, 3.3 V zero delay buffer designed to  
distribute highspeed clocks. It accepts one reference input and drives  
out five lowskew clocks. It is available in a 8 pin package.  
The 1H version of the NB2305A operates at up to 133 MHz, and  
has higher drive than the 1 devices. All parts have onchip PLL’s that  
lock to an input clock on the REF pin. The PLL feedback is onchip  
and is obtained from the CLKOUT pad.  
http://onsemi.com  
MARKING  
DIAGRAMS*  
Multiple NB2305A devices can accept the same input clock and  
distribute it. In this case the skew between the outputs of the two  
devices is guaranteed to be less than 700 ps.  
All outputs have less than 200 ps of cycletocycle jitter. The input  
and output propagation delay is guaranteed to be less than 350 ps, and  
the output to output skew is guaranteed to be less than 250 ps.  
The NB2305A is available in two different configurations, as shown  
in the ordering information table. The NB2305A1 is the base part. The  
NB2305Ax1H* is the high drive version of the 1 and its rise and fall  
times are much faster than 1 part.  
8
8
XXXX  
ALYW  
G
1
SOIC8  
D SUFFIX  
CASE 751  
1
8
8
XXX  
ALYWG  
G
1
Features  
TSSOP8  
DT SUFFIX  
CASE 948J  
15 MHz to 133 MHz Operating Range, Compatible with CPU and  
PCI Bus Frequencies  
1
Zero Input Output Propagation Delay  
Multiple LowSkew Outputs  
OutputOutput Skew Less than 250 ps  
DeviceDevice Skew Less than 700 ps  
One Input Drives 5 Outputs  
XXXX = Device Code  
A
L
Y
W
G
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= PbFree Package  
(Note: Microdot may be in either location)  
Less than 200 ps CycletoCycle Jitter is Compatible with PentiumR  
Based Systems  
*For additional marking information, refer to  
Application Note AND8002/D.  
Available in 8 Pin, 150 mil SOIC Package and 8 Pin TSSOP 4.4 mm  
3.3 V Operation, Advanced 0.35 CMOS Technology  
These are PbFree Devices  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 6 of this data sheet.  
*x = C for Commercial; I for Industrial.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 Rev. 5  
NB2305A/D  

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