5秒后页面跳转
NB2308AI1DTG PDF预览

NB2308AI1DTG

更新时间: 2024-01-04 06:21:52
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
13页 206K
描述
Zero Delay Buffer, 3.3 V, Eight Output, TSSOP-16, 96-TUBE

NB2308AI1DTG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.23系列:2308
输入调节:STANDARDJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:5 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.008 A
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:16
实输出次数:8最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.2 ns座面最大高度:1.2 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:4.4 mm最小 fmax:133.3 MHz
Base Number Matches:1

NB2308AI1DTG 数据手册

 浏览型号NB2308AI1DTG的Datasheet PDF文件第2页浏览型号NB2308AI1DTG的Datasheet PDF文件第3页浏览型号NB2308AI1DTG的Datasheet PDF文件第4页浏览型号NB2308AI1DTG的Datasheet PDF文件第5页浏览型号NB2308AI1DTG的Datasheet PDF文件第6页浏览型号NB2308AI1DTG的Datasheet PDF文件第7页 
NB2308A  
3.3 V Zero Delay  
Clock Buffer  
The NB2308A is a versatile, 3.3 V zero delay buffer designed to  
distribute highspeed clocks. It is available in a 16 pin package. The  
part has an onchip PLL which locks to an input clock presented on  
the REF pin. The PLL feedback is required to be driven to FBK pin,  
and can be obtained from one of the outputs. The inputtooutput  
propagation delay is guaranteed to be less than 250 ps, and the  
outputtooutput skew is guaranteed to be less than 200 ps.  
The NB2308A has two banks of four outputs each, which can be  
controlled by the select inputs as shown in the Select Input Decoding  
Table. If all the output clocks are not required, Bank B can be  
threestated. The select input also allows the input clock to be directly  
applied to the outputs for chip and system testing purposes.  
Multiple NB2308A devices can accept the same input clock and  
distribute it. In this case the skew between the outputs of the two  
devices is guaranteed to be less than 700 ps.  
http://onsemi.com  
MARKING  
DIAGRAMS*  
16  
1
16  
XXXXXXXXXG  
AWLYWW  
1
SOIC16  
D SUFFIX  
CASE 751B  
The NB2308A is available in five different configurations (Refer to  
NB2308A Configurations Table). The NB2308Ax1* is the base part,  
where the output frequencies equal the reference if there is no counter  
in the feedback path. The NB2308Ax1H is the highdrive version of  
the 1 and the rise and fall times on this device are much faster.  
The NB2308Ax2 allows the user to obtain 2X and 1X frequencies  
on each output bank. The exact configuration and output frequencies  
depends on which output drives the feedback pin. The NB2308Ax3  
allows the user to obtain 4X and 2X frequencies on the outputs.  
The NB2308Ax4 enables the user to obtain 2X clocks on all outputs.  
Thus, the part is extremely versatile, and can be used in a variety of  
applications.  
16  
XXXX  
XXXX  
ALYWG  
G
16  
1
TSSOP16  
DT SUFFIX  
CASE 948F  
1
XXXX = Device Code  
= Assembly Location  
WL, L = Wafer Lot  
= Year  
A
Y
The NB2308Ax5H is a highdrive version with REF/2 on both  
banks.  
WW, W = Work Week  
G or G = PbFree Package  
(Note: Microdot may be in either location)  
Features  
Zero Input Output Propagation Delay, Adjustable by Capacitive  
*For additional marking information, refer to  
Application Note AND8002/D.  
Load on FBK Input  
Multiple Configurations Refer to NB2308A Configurations Table  
Input Frequency Range: 15 MHz to 133 MHz  
Multiple LowSkew Outputs  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 9 of this data sheet.  
OutputOutput Skew Less than 200 ps  
DeviceDevice Skew Less than 700 ps  
Two banks of four outputs, threestateable by two select inputs  
Less than 200 ps CycletoCycle Jitter  
Available in 16pin SOIC and TSSOP Packages  
3.3V operation  
Advanced 0.35 CMOS Technology  
PbFree Packages are Available**  
*x = C for Commercial; I for Industrial.  
**For additional information on our PbFree strategy and soldering details,  
please download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
November, 2005 Rev. 2  
NB2308A/D  

NB2308AI1DTG 替代型号

型号 品牌 替代类型 描述 数据表
NB2308AI1DTR2G ONSEMI

完全替代

Zero Delay Buffer, 3.3 V, Eight Output, TSSOP-16, 2500-REEL
NB2308AI1HDTG ONSEMI

类似代替

Zero Delay Buffer, 3.3 V, Eight Output, TSSOP-16, 96-TUBE
2308-1HPGGI8 IDT

类似代替

3.3V ZERO DELAY CLOCK MULTIPLIER

与NB2308AI1DTG相关器件

型号 品牌 获取价格 描述 数据表
NB2308AI1DTR2G ONSEMI

获取价格

Zero Delay Buffer, 3.3 V, Eight Output, TSSOP-16, 2500-REEL
NB2308AI1H ONSEMI

获取价格

3.3 V Zero Delay Clock Buffer
NB2308AI1HDG ROCHESTER

获取价格

2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16, LEAD
NB2308AI1HDTG ONSEMI

获取价格

Zero Delay Buffer, 3.3 V, Eight Output, TSSOP-16, 96-TUBE
NB2308AI2 ONSEMI

获取价格

3.3 V Zero Delay Clock Buffer
NB2308AI2DG ROCHESTER

获取价格

2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16, LEAD
NB2308AI2DTG ONSEMI

获取价格

Zero Delay Buffer, 3.3 V, Eight Output, TSSOP-16, 96-TUBE
NB2308AI2DTR2G ROCHESTER

获取价格

2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16, LEAD
NB2308AI3 ONSEMI

获取价格

3.3 V Zero Delay Clock Buffer
NB2308AI3DG ONSEMI

获取价格

3.3 V Zero Delay Clock Buffer