NB2305AI1DTG

更新时间： 2024-11-20 03:03:31

品牌	Logo	应用领域
安森美 - ONSEMI		时钟
页数	文件大小	规格书
8页	134K
描述
3.3 V Zero Delay Clock Buffer

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NB2305AI1DTG 数据手册

NB2305A

3.3 V Zero Delay

Clock Buffer

The NB2305A is a versatile, 3.3 V zero delay buffer designed to

distribute high−speed clocks. It accepts one reference input and drives

out five low−skew clocks. It is available in a 8 pin package.

The −1H version of the NB2305A operates at up to 133 MHz, and

has higher drive than the −1 devices. All parts have on−chip PLL’s that

lock to an input clock on the REF pin. The PLL feedback is on−chip

and is obtained from the CLKOUT pad.

http://onsemi.com

MARKING

DIAGRAMS*

Multiple NB2305A devices can accept the same input clock and

distribute it. In this case the skew between the outputs of the two

devices is guaranteed to be less than 700 ps.

All outputs have less than 200 ps of cycle−to−cycle jitter. The input

and output propagation delay is guaranteed to be less than 350 ps, and

the output to output skew is guaranteed to be less than 250 ps.

The NB2305A is available in two different configurations, as shown

in the ordering information table. The NB2305A1 is the base part. The

NB2305Ax1H* is the high drive version of the −1 and its rise and fall

times are much faster than −1 part.

XXXX

ALYW

SOIC−8

D SUFFIX

CASE 751

XXX

ALYWG

Features

TSSOP−8

DT SUFFIX

CASE 948J

• 15 MHz to 133 MHz Operating Range, Compatible with CPU and

PCI Bus Frequencies

• Zero Input − Output Propagation Delay

• Multiple Low−Skew Outputs

• Output−Output Skew Less than 250 ps

• Device−Device Skew Less than 700 ps

• One Input Drives 5 Outputs

XXXX = Device Code

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

(Note: Microdot may be in either location)

• Less than 200 ps Cycle−to−Cycle Jitter is Compatible with PentiumR

Based Systems

*For additional marking information, refer to

Application Note AND8002/D.

• Available in 8 Pin, 150 mil SOIC Package and 8 Pin TSSOP 4.4 mm

• 3.3 V Operation, Advanced 0.35 ꢀ CMOS Technology

• These are Pb−Free Devices

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

*x = C for Commercial; I for Industrial.

Publication Order Number:

November, 2006 − Rev. 5

NB2305A/D

12 3 4 5 6 7 8

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NB2305AI1DTG 替代型号

型号	品牌	替代类型	描述	数据表
NB2305AI1DTR2G	ONSEMI	完全替代	3.3 V Zero Delay Clock Buffer
NB2305AI1HDTR2G	ONSEMI	类似代替	3.3 V Zero Delay Clock Buffer
NB2305AI1HDTG	ONSEMI	类似代替	3.3 V Zero Delay Clock Buffer

与NB2305AI1DTG相关器件

型号	品牌	获取价格	描述	数据表
NB2305AI1DTR2G	ONSEMI	获取价格	3.3 V Zero Delay Clock Buffer
NB2305AI1HDG	ONSEMI	获取价格	3.3 V Zero Delay Clock Buffer
NB2305AI1HDR2G	ONSEMI	获取价格	3.3 V Zero Delay Clock Buffer
NB2305AI1HDT	ONSEMI	获取价格	IC 2305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, TSS
NB2305AI1HDTG	ONSEMI	获取价格	3.3 V Zero Delay Clock Buffer
NB2305AI1HDTR2	ONSEMI	获取价格	2305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, TSSOP-
NB2305AI1HDTR2G	ONSEMI	获取价格	3.3 V Zero Delay Clock Buffer
NB2308A	ONSEMI	获取价格	3.3 V Zero Delay Clock Buffer
NB2308AC1DR2G	ONSEMI	获取价格	2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16, LEAD
NB2308AC1HDTR2G	ONSEMI	获取价格	2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16, LEAD

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