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N82C42PD PDF预览

N82C42PD

更新时间： 2024-02-20 06:32:26
品牌 Logo 应用领域
英特尔 - INTEL 微控制器
页数 文件大小 规格书
25页 347K
描述
UNIVERSAL PERIPHERAL INTERFACE CHMOS 8-BIT SLAVE MICROCONTROLLER

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N82C42PD 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Active零件包装代码：LCC
包装说明：PLASTIC, LCC-44针数：44
Reach Compliance Code：unknown风险等级：5.52
Is Samacsys：N具有ADC：NO
位大小：8DAC 通道：NO
DMA 通道：NOJESD-30 代码：S-PQCC-J44
JESD-609代码：e0I/O 线路数量：16
端子数量：44PWM 通道：NO
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：COMMERCIAL
ROM可编程性：MROM速度：12.5 MHz
最大供电电压：5 V最小供电电压：5 V
表面贴装：YES端子面层：TIN LEAD
端子形式：J BEND端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIEDuPs/uCs/外围集成电路类型：MICROCONTROLLER
Base Number Matches：1

N82C42PD 数据手册

 浏览型号N82C42PD的Datasheet PDF文件第2页浏览型号N82C42PD的Datasheet PDF文件第3页浏览型号N82C42PD的Datasheet PDF文件第4页浏览型号N82C42PD的Datasheet PDF文件第5页浏览型号N82C42PD的Datasheet PDF文件第6页浏览型号N82C42PD的Datasheet PDF文件第7页 
UPI-C42/UPI-L42  
UNIVERSAL PERIPHERAL INTERFACE  
CHMOS 8-BIT SLAVE MICROCONTROLLER  
Y
Y
Y
Pin, Software and Architecturally  
One 8-Bit Status and Two Data  
Registers for Asynchronous Slave-to-  
Master Interface  
Compatible with all UPI-41 and UPI-42  
Products  
Y
Y
Low Voltage Operation with the UPI-  
L42  
Ð Full 3.3V Support  
Fully Compatible with all Intel and Most  
Other Microprocessor Families  
Interchangeable ROM and OTP EPROM  
Versions  
Y
Y
Y
Y
Hardware A20 Gate Support  
Y
Y
Y
Y
Suspend Power Down Mode  
Expandable I/O  
Security Bit Code Protection Support  
Sync Mode Available  
8-Bit CPU plus ROM/OTP EPROM, RAM,  
I/O, Timer/Counter and Clock in a  
Single Package  
Over 90 Instructions: 70% Single Byte  
Quick Pulse Programming Algorithm  
Ð Fast OTP Programming  
Y
Y
4096 x 8 ROM/OTP, 256 x 8 RAM 8-Bit  
Timer/Counter, 18 Programmable I/O  
Pins  
Y
Available in 40-Lead Plastic, 44-Lead  
Plastic Leaded Chip Carrier, and  
44-Lead Quad Flat Pack Packages  
Ý
(See Packaging Spec., Order 240800, Package Type P, N,  
and S)  
DMA, Interrupt, or Polled Operation  
Supported  
The UPI-C42 is an enhanced CHMOS version of the industry standard Intel UPI-42 family. It is fabricated on  
Intel’s CHMOS III-E process. The UPI-C42 is pin, software, and architecturally compatible with the NMOS UPI  
family. The UPI-C42 has all of the same features of the NMOS family plus a larger user programmable memory  
array (4K), hardware A20 gate support, and lower power consumption inherent to a CHMOS product.  
The UPI-L42 offers the same functionality and socket compatibility as the UPI-C42 as well as providing low  
voltage 3.3V operation.  
The UPI-C42 is essentially a ‘‘slave’’ microcontroller, or a microcontroller with a slave interface included on the  
chip. Interface registers are included to enable the UPI device to function as a slave peripheral controller in the  
MCS Modules and iAPX family, as well as other 8-, 16-, and 32-bit systems.  
To allow full user flexibility, the program memory is available in ROM and One-Time Programmable EPROM  
(OTP).  
290414–1  
290414–3  
Figure 1. DIP Pin  
290414–2  
Figure 3. QFP Pin Configuration  
Configuration  
Figure 2. PLCC Pin Configuration  
*Other brands and names are the property of their respective owners.  
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or  
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make  
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.  
©
COPYRIGHT INTEL CORPORATION, 1996  
December 1995  
Order Number: 290414-003  
1234567...25

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