N82C42PD

更新时间： 2024-01-12 14:35:28

品牌	Logo	应用领域
英特尔 - INTEL		微控制器
页数	文件大小	规格书
25页	347K
描述
UNIVERSAL PERIPHERAL INTERFACE CHMOS 8-BIT SLAVE MICROCONTROLLER

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技术参数
数据手册

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N82C42PD 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	LCC
包装说明：	PLASTIC, LCC-44	针数：	44
Reach Compliance Code：	unknown	风险等级：	5.52
Is Samacsys：	N	具有ADC：	NO
位大小：	8	DAC 通道：	NO
DMA 通道：	NO	JESD-30 代码：	S-PQCC-J44
JESD-609代码：	e0	I/O 线路数量：	16
端子数量：	44	PWM 通道：	NO
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	COMMERCIAL
ROM可编程性：	MROM	速度：	12.5 MHz
最大供电电压：	5 V	最小供电电压：	5 V
表面贴装：	YES	端子面层：	TIN LEAD
端子形式：	J BEND	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	uPs/uCs/外围集成电路类型：	MICROCONTROLLER
Base Number Matches：	1

N82C42PD 数据手册

UPI-C42/UPI-L42

thereby providing additional user programmable

memory space. This feature is enabled by the

A20EN instruction and remains enabled until the de-

vice is reset. It is important to note that the execu-

tion of the A20EN instruction redefines Port 2, bit 1

as a pure output pin with read only characteristics.

The state of this pin can be modified only through a

valid ‘‘D1’’ command sequence (see Table 1). Once

enabled, the A20 logic will process a ‘‘D1’’ com-

mand sequence (write to output port) by setting/re-

setting the A20 bit on port 2, bit 1 (P2.1) without

requiring service from the internal CPU. The host

can directly control the status of the A20 bit. At no

time during this host interface transaction will the

IBF flag in the status register be activated. Table 1

gives several possible GATEA20 command/data se-

quences and UPI-C42 responses.

SUSPEND

The execution of the suspend instruction (82h or

E2h) causes the UPI-C42 to enter the suspend

mode. In this mode of operation the oscillator is not

running and the internal CPU operation is stopped.

The UPI-C42 consumes 40 mA in the suspend

mode. This mode can only be exited by RESET.

CPU operation will begin from PC

UPI-C42 exits from the suspend power down mode.

000h when the

Suspend Mode Summary

Oscillator Not Running

CPU Operation Stopped

Ports Tristated with Weak ( 2–10 mA) Pull-Up

Micropower Mode (I

40 mA)

Table 1. D1 Command Sequences

This mode is exited by RESET

A0 R/W DB Pins IBF A20

Comments

(1)

D1h

DFh

FFH

Set A20 Sequence

Only DB1 Is Processed

(2)

D1h

DDh

FFh

Clear A20 Sequence

D1h

DFh

FFh

Double Trigger Set

Sequence

D1h

Invalid Sequence

No Change in State

of A20 Bit

(3)

XXh

DDh

NOTES:

1. Indicates that P2.1 remains at the previous logic level.

2. Only FFh commands in a valid A20 sequence have no

effect on IBF. An FFh issued at any other time will activate

IBF.

3. Any command except D1.

The above sequences assume that the GATEA20

logic has been enabled via the A20EN instruction.

As noted, only the value on DB 1 (data bus, bit 1) is

processed. This bit will be directly passed through to

P2.1 (port 2, bit 1).

1...4 5 678 9 10...25

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