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N01S830HAT22IT PDF预览

N01S830HAT22IT

更新时间： 2024-02-23 11:03:34
品牌 Logo 应用领域
安森美 - ONSEMI 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
13页 99K
描述
1 Mb Ultra-Low Power Serial SRAM

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N01S830HAT22IT 技术参数

是否无铅： 不含铅生命周期：Active
包装说明：TSSOP-8Reach Compliance Code：compliant
Factory Lead Time：96 weeks风险等级：5.77
JESD-30 代码：R-PDSO-G8JESD-609代码：e3
长度：4.4 mm内存密度：1048576 bit
内存集成电路类型：STANDARD SRAM内存宽度：8
湿度敏感等级：3功能数量：1
端子数量：8字数：131072 words
字数代码：128000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：128KX8封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH并行/串行：SERIAL
座面最大高度：1.1 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin (Sn)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
宽度：3 mmBase Number Matches：1

N01S830HAT22IT 数据手册

 浏览型号N01S830HAT22IT的Datasheet PDF文件第1页浏览型号N01S830HAT22IT的Datasheet PDF文件第2页浏览型号N01S830HAT22IT的Datasheet PDF文件第3页浏览型号N01S830HAT22IT的Datasheet PDF文件第5页浏览型号N01S830HAT22IT的Datasheet PDF文件第6页浏览型号N01S830HAT22IT的Datasheet PDF文件第7页 
N01S830HA, N01S830BA  
DEVICE OPERATIONS  
Read Operation  
The serial SRAM Read operation is started by by enabling  
CS low. First, the 8-bit Read instruction is transmitted to the  
device through the SI (or SIO0-3) pin(s) followed by the  
24-bit address with the 7 MSBs of the address being “don’t  
care” bits and ignored. In SPI mode, after the READ  
instruction and address bits are sent, the data stored at that  
address in memory is shifted out on the SO pin after the  
output valid time. Additional “dummy” clock cycles (four in  
DUAL and two in QUAD) are required to follow the  
instruction and address inputs prior to the data being driven  
out on the SIO0-3 pins while operating in these two modes.  
By continuing to provide clock cycles to the device, data  
can continue to be read out of the memory array in  
sequentially. The internal address pointer is automatically  
incremented to the next higher address after each byte of  
data is read out until the highest memory address is reached.  
When the highest memory address is reached, 1FFFFh, the  
address pointer wraps to the address 00000h. This allows the  
read cycles to be continued indefinitely. All Read operations  
are terminated by pulling CS high.  
CS  
SCK  
0
1
2
3
4
5
6
7
8
9
10 11  
29 30 31 32 33 34 35 36 37 38 39  
Instruction  
24−bit address  
23 22 21 20  
SI  
0
0
0
0
0
0
1
1
2
1
0
Data Out  
High−Z  
7
6
5
4
3
2
1
0
SO  
Figure 2. SPI Read Sequence (Single Byte)  
CS  
SCK  
0
1
2
3
4
5
6
7
8
9
10 11  
29 30 31 32 33 34 35 36 37 38 39  
Instruction  
24−bit address  
SI  
0
0
0
0
0
0
1
1
23 22 21 20  
ADDR 1  
2
1
0
Don’t Care  
Data Out from ADDR 1  
High−Z  
7
6
5
4
3
2
1
0
SO  
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55  
Don’t Care  
Data Out from ADDR 3  
Data Out from ADDR 2  
Data Out from ADDR n  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
...  
Figure 3. SPI Read Sequence (Sequential Bytes)  
www.onsemi.com  
4
1234567...13

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