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MX26L6413TI-90 PDF预览

MX26L6413TI-90

更新时间: 2024-11-22 19:55:19
品牌 Logo 应用领域
旺宏电子 - Macronix 光电二极管内存集成电路
页数 文件大小 规格书
37页 618K
描述
Flash, 4MX16, 90ns, PDSO48, 12 X 20 MM, PLASTIC, MO-142, TSOP1-48

MX26L6413TI-90 数据手册

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ADVANCED INFORMATION  
MX26L6413  
64M-BIT[4Mx16]CMOS  
MULTIPLE-TIME-PROGRAMMABLEEPROM  
FEATURES  
4,194,304 x 16 byte structure  
Single Power Supply Operation  
- 2.7 to 3.6 volt for read, erase andprogram  
operation  
Minimum 100 erase/program cycle  
Status Reply  
- Data polling & Toggle bits provide detection of  
programanderaseoperationcompletion  
12V ACC input pin provides accelerated program  
capability  
Low Vcc write inhibit is equal to or less than 2.5V  
Compatible with JEDEC standard  
HighPerformance  
- Fast access time: 90/120ns (typ.)  
- Fast program time: 140s/chip (typ.)  
- Fast erase time: 150s/chip (typ.)  
LowPowerConsumption  
Output voltages and input voltages on the device is  
deterined by the voltage on the VI/O pin.  
- VI/O voltage range:1.65V~3.6V  
10 years data retention  
Package  
- Low active read current: 17mA (typ.) at 5MHz  
- 48-Pin TSOP  
- Low standby current: 30uA (typ.)  
- 63-Ball CSP  
GENERAL DESCRIPTION  
MXIC's MTP EPROMTM technology reliably stores  
memory contents even after 100 erase and program  
cycles. The MXIC cell is designed to optimize the erase  
andprogrammechanisms.Inaddition,thecombinationof  
advanced tunnel oxide processing and low internal  
electric fields for erase and programming operations  
produces reliable cycling.  
The MX26L6413 is a 64M bit MTP EPROMTM organized  
as 4M bytes of 16 bits. MXIC's MTP EPROMTM offer the  
most cost-effective and reliable read/write non-volatile  
randomaccessmemory.TheMX26L6413ispackagedin  
48-pin TSOP, 48-ball CSP amd 63-ball CSP. It is  
designedtobereprogrammedanderasedinsystemorin  
standardEPROMprogrammers.  
The MX26L6413 uses a 2.7V to 3.6V VCC supply to  
perform the High Reliability Erase and auto Program/  
Erasealgorithms.  
The standard MX26L6413 offers access time as fast as  
90ns,allowingoperationofhigh-speedmicroprocessors  
without wait states. To eliminate bus contention, the  
MX26L6413 has separate chip enable (CE) and output  
enable OE controls. MXIC's MTP EPROMTM augment  
EPROMfunctionalitywithin-circuitelectricalerasureand  
programming.TheMX26L6413usesacommandregister  
to manage this functionality.  
Thehighestdegreeoflatch-upprotectionisachievedwith  
MXIC'sproprietarynon-epiprocess.Latch-upprotection  
isprovedforstressesupto100milliampsonaddressand  
data pin from -1V to VCC +1V.  
P/N:PM0914  
REV. 0.1, NOV. 20, 2002  
1

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