Document Number VYBRIDFSERIESEC
Rev 8, 11/2014
Freescale Semiconductor
Data Sheet: Technical Data
VYBRIDFSERIESEC
VF6xx, VF5xx, VF3xx
Features
• Debug
– Standard JTAG
– 16-bit Trace port
• Operating characteristics
– Voltage range 3 V to 3.6 V
– Temperature range(ambient) -40 °C to 85 °C
• Timers
– Motor control/general purpose timer (FTM)
– Periodic Interrupt Timers (PITs)
– Low-power timer (LPTMR0)
– IEEE 1588 Timer per MAC interface (part of
Ethernet Subsystem)
• ARM® Cortex® A5 Core features
– Up to 500 MHz ARM Cortex A5
– 32 KB/32 KB I/D L1 Cache
– 1.6 DMIPS/MHz based on ARMv7 architecture
– NEON™ MPE (Media Processing Engine) Co-
processor
• Communications
– Double Precision Floating Point Unit
– 512 KB L2 cache (on selected part numbers only)
– Six Universal asynchronous receivers/transmitters
(UART)/Serial communications interface (SCI) with
LIN, ISO7816, IrDA, and hardware flow control
– Four Deserial Serial peripheral interface (DSPI)
– Four Inter-Integrated Circuit (I2C) with SMBUS
support
– Dual USB OTG Controller + PHY
– Dual 4/8 bit Secure Digital Host controller
– Dual 10/100 Ethernet with L2 Switch (IEEE 1588)
– Dual FlexCAN3
• ARM Cortex M4 Core features
– Up to 167 MHz ARM Cortex M4
– Integrated DSP capability
– 64 KB Tightly Coupled Memory (TCM)
– 16 KB/16 KB I/D L1 Cache
– 1.25 DMIPS/MHz based on ARMv7 architecture
• Clocks
– 24 MHz crystal oscillator
– 32 kHz crystal oscillator
– Internal reference clocks (128 KHz and 24 MHz)
– Phase Locked Loops (PLLs)
– Low Jitter Digital PLLs
• Security
– ARM TrustZone including the TZ architecture
– Cryptographic Acceleration and Assurance Module,
incorporates 16 KB secure RAM (CAAM)
– Secure Non-Volatile Storage, including Secure Real
Time Clock (SNVS)
– Real Time Integrity Checker (RTIC)
– Tamper detection - supported by external pins, on-
chip clock monitors, voltage and temperature
tampers
– TrustZone Watchdog (TZ WDOG)
– Trust Zone Address Space Controller
– Central Security Unit
– Secure JTAG
– High Assurance Boot (HAB) with support for
encrypted boot
• System debug, protection, and power management
– Various stop, wait, and run modes to provide low
power based on application needs
– Peripheral clock enable register can disable clocks to
unused modules, thereby reducing currents
– Low voltage warning and detect with selectable trip
points
– Illegal opcode and illegal address detection with
programmable reset or processor exception response
– Hardware CRC module to support fast cyclic
redundancy checks (CRC)
– 128-bit unique chip identifier
– Hardware watchdog
– External Watchdog Monitor (EWM)
– Dual DMA controller with 32 channels (with
DMAMUX)
• Memory Interfaces
– 8/16 bit DRAM Controller with support for
LPDDR2/DDR3 - Up to 400 MHz (ECC supported
for 8-bit only and not 16-bit)
– 8/16 bit NAND Flash controller with ECC
– 8/16/32 bit External bus (Flexbus)
– Dual Quad SPI with XIP (Execute-In-Place)
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
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