MT9162AN1

更新时间： 2024-01-12 16:23:56

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		解码器编解码器电信集成电路电信电路光电二极管
页数	文件大小	规格书
22页	569K
描述
5 Volt Single Rail Codec

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技术参数
数据手册

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MT9162AN1 技术参数

生命周期：	Transferred	包装说明：	SSOP,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.69	Is Samacsys：	N
压伸定律：	A/MU-LAW	滤波器：	YES
JESD-30 代码：	R-PDSO-G20	JESD-609代码：	e3
长度：	7.2 mm	功能数量：	1
端子数量：	20	工作模式：	SYNCHRONOUS/ASYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, SHRINK PITCH
认证状态：	Not Qualified	座面最大高度：	2 mm
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	PROGRAMMABLE CODEC
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	宽度：	5.3 mm
Base Number Matches：	1

MT9162AN1 数据手册

MT9162

Data Sheet

SSI Mode

The SSI BUS consists of input and output serial data streams named Din and Dout respectively, a Clock input

signal (CLOCKin), and a framing strobe input (STB). A 4.096 MHz master clock is also required for SSI operation if

the bit clock is less than 512 kHz. The timing requirements for SSI are shown in Figures 5 & 6.

In SSI mode the MT9162 supports only B-Channel operation. Hence, in SSI mode transmit and receive B-Channel

data are always in the channel defined by the STB input.

The data strobe input STB determines the 8-bit timeslot used by the device for both transmit and receive data. This

is an active high signal with an 8 kHz repetition rate.

SSI operation is separated into two categories based upon the data rate of the available bit clock. If the bit clock is

512 kHz or greater then it is used directly by the internal MT9162 functions allowing synchronous operation. If the

available bit clock is 128 kHz or 256 kHz, then a 4096 kHz master clock is required to derive clocks for the internal

MT9162 functions.

Applications where Bit Clock (BCL) is below 512 kHz are designated as asynchronous. The MT9162 will re-align its

internal clocks to allow operation when the external master and bit clocks are asynchronous. Control pins CSL2,

CSL1 and CSL0 are used to program the bit rates.

Filter/Codec and Analog Interface

Serial Port

Aout +

Aout-

PCM

-2.05 dB

Receive

Filter Gain

0 dB

Decoder

2.05 dB

D_in

Receiver

20kΩ

Driver

PCM

AIN+

Transmit

Gain

8.42 dB

Transmit Filter

Analog

Input

Transmit Gain

-0.37 dB

Encoder

-2.05 dB

Gain

D_out

Gain

AIN-

0dB

0 to +7 dB

(1 dB steps)

Internal To Device

External To Device

Figure 3 - Audio Gain Partitioning

For synchronous operation, data is sampled from Din, on the falling edge of BCL during the time slot defined by the

STB input. Data is made available, on Dout, on the rising edge of BCL during the time slot defined by the STB input.

Dout is tri-stated at all times when STB is not true. If STB is valid, then quiet code will be transmitted on Dout during

the valid strobe period. There is no frame delay through the PCM serial circuit for synchronous operation.

Zarlink Semiconductor Inc.

1 2 3 456 7 8...22

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与MT9162AN1相关器件

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MT9162AS	MITEL	ISO2-CMOS 5 Volt Single Rail Codec	获取价格
MT9162AS	ZARLINK	5 Volt Single Rail Codec	获取价格
MT91633AS	MICROSEMI	Telecom IC, PDSO16,	获取价格
MT91633AS	ZARLINK	Telecom Circuit, 1-Func, PDSO16, SOIC-16	获取价格
MT91634AQ	MICROSEMI	Telecom IC, PDSO36,	获取价格
MT9171	MITEL	ISO2-CMOS ST-BUS⑩ FAMILY Digital Subscriber I	获取价格

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