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MT9123AE PDF预览

MT9123AE

更新时间: 2024-11-28 22:53:15
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MITEL 电信集成电路光电二极管综合业务数字网
页数 文件大小 规格书
32页 193K
描述
CMOS Dual Voice Echo Canceller

MT9123AE 数据手册

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CMOS MT9123  
Dual Voice Echo Canceller  
Preliminary Information  
ISSUE 1  
October 1996  
Features  
Dual channel 64ms or single channel 128ms  
echo cancellation  
Ordering Information  
MT9123AP  
MT9123AE  
28 Pin PLCC  
28 Pin PDIP  
Conforms to ITU-T G.165 requirements  
Narrow-band signal detection  
-40 °C to + 85 °C  
Programmable double-talk detection threshold  
Description  
Non-linear processor with adaptive suppression  
threshold and comfort noise insertion  
The MT9123 Voice Echo Canceller implements a  
cost effective solution for telephony voice-band echo  
Offset nulling of all PCM channels  
cancellation  
conforming  
to  
ITU-T  
G.165  
Controllerless mode or Controller mode with  
serial interface  
requirements. The MT9123 architecture contains two  
echo cancellers which can be configured to provide  
dual channel 64 millisecond echo cancellation or  
single channel 128 millisecond echo cancellation.  
ST-BUS or variable-rate SSI PCM interfaces  
Selectable µ/A-Law ITU-T G.711; µ/A-Law Sign  
Mag; linear 2’s complement  
Per channel selectable 12 dB attenuator  
Transparent data transfer and mute option  
19.2 MHz master clock operation  
The MT9123 operates in two major modes:  
Controller or Controllerless. Controller mode allows  
access to an array of features for customizing the  
MT9123 operation. Controllerless mode is for  
applications where default register settings are  
sufficient.  
Applications  
Wireless Telephony  
Trunk echo cancellers  
Linear/  
µ/A-Law  
Non-Linear  
Processor  
Offset  
Null  
Linear/  
µ/A-Law  
Sin  
+
Sout  
-
Microprocessor  
Interface  
Double-Talk  
Detector  
Programmable  
Bypass  
Narrow-Band  
Detector  
Offset  
Null  
12dB  
Attenuator  
Linear/  
µ/A-Law  
Linear/  
µ/A-Law  
Rin  
ENA1  
ENB1  
Rout  
ENA2  
ENB2  
CONFIG1  
CONFIG2  
S1/DATA1  
S2/DATA2  
S3/CS  
Echo Canceller A  
Echo Canceller B  
NLP  
LAW  
FORMAT  
IC3  
IC4  
S4/SCLK  
IC1  
IC2  
VDD  
VSS  
PWRDN  
F0od  
F0i  
BCLK/C4i  
MCLK  
Figure 1 - Functional Block Diagram  
8-45  

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