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MT9126 PDF预览

MT9126

更新时间: 2024-11-29 04:14:11
品牌 Logo 应用领域
MITEL 转换器PC
页数 文件大小 规格书
22页 315K
描述
CMOS Quad ADPCM Transcoder

MT9126 数据手册

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CMOS MT9126  
Quad ADPCM Transcoder  
Preliminary Information  
ISSUE 2  
May 1995  
Features  
Full duplex transcoder with four encode  
channels and four decode channels  
Ordering Information  
MT9126AE  
MT9126AS  
28 Pin Plastic DIP  
28 Pin SOIC  
32 kb/s, 24 kb/s and 16 kb/s ADPCM coding  
complying with ITU-T (previously CCITT) G.726  
(without 40 kb/s), and ANSI T1.303-1989  
-40 °C to +85 °C  
Low power operation, 25 mW typical  
Description  
Asynchronous 4.096 MHz master clock  
operation  
The Quad ADPCM Transcoder is a low power,  
CMOS device capable of four encode and four  
decode functions per frame. Four 64 kbit/s PCM  
octets are compressed into four 32, 24 or 16 kbit/s  
ADPCM words, and four 32, 24 or 16 kbit/s ADPCM  
words are expanded into four 64 kbit/s PCM octets.  
The 32, 24 and 16 kbit/s ADPCM transcoding  
SSI and ST-BUS interface options  
Transparent PCM bypass  
Transparent ADPCM bypass  
Linear PCM code  
No microprocessor control required  
Simple interface to Codec devices  
Pin selectable µ−Law or A-Law operation  
algorithms  
utilized  
conform  
to  
ITU-T  
Recommendation G.726 (excluding 40 kbit/s), and  
ANSI T1.303 - 1989.  
Pin selectable ITU-T or signed magnitude PCM  
coding  
Switching, on-the-fly, between 32 kbit/s and 24 kbit/s  
ADPCM, is possible by controlling the appropriate  
mode select (MS1 - MS6) control pins. All optional  
functions of the device are pin selectable allowing a  
simple interface to industry standard codecs, digital  
phone devices and Layer 1 transceivers. Linear  
coded PCM is provided to facilitate external DSP  
functions .  
Single 5 volt power supply  
Applications  
Pair gain  
Voice mail systems  
Wireless telephony systems  
PCMo1  
PCMi1  
Full Duplex  
ADPCMi  
ADPCMo  
ADPCM  
I/O  
PCM  
I/O  
Quad  
Transcoder  
PCMo2  
PCMi2  
ENB1  
ENB2/F0od  
BCLK  
F0i  
MCLK  
Timing  
C2o  
EN1  
EN2  
Control Decode  
VDD VSS PWRDN IC  
MS1 MS2 MS3  
FORMAT MS4 MS5 MS6 LINEAR SEL  
A/µ  
Figure 1 - Functional Block Diagram  
8-33  

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