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MT89L86ANR1 PDF预览

MT89L86ANR1

更新时间： 2024-02-06 10:38:46
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 电信光电二极管电信集成电路
页数 文件大小 规格书
44页 427K
描述
Digital Time Switch, CMOS, PDSO48, 0.300 INCH, LEAD FREE, MO-118AA, SSOP-48

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MT89L86ANR1 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP, SSOP48,.4针数：48
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.65JESD-30 代码：R-PDSO-G48
JESD-609代码：e3长度：15.88 mm
功能数量：1端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP48,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
座面最大高度：2.79 mm子类别：Other Telecom ICs
最大压摆率：10 mA标称供电电压：3.3 V
表面贴装：YES技术：CMOS
电信集成电路类型：DIGITAL TIME SWITCH温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.64 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：7.49 mm
Base Number Matches：1

MT89L86ANR1 数据手册

 浏览型号MT89L86ANR1的Datasheet PDF文件第2页浏览型号MT89L86ANR1的Datasheet PDF文件第3页浏览型号MT89L86ANR1的Datasheet PDF文件第4页浏览型号MT89L86ANR1的Datasheet PDF文件第6页浏览型号MT89L86ANR1的Datasheet PDF文件第7页浏览型号MT89L86ANR1的Datasheet PDF文件第8页 
MT89L86  
Data Sheet  
Pin Description (continued)  
Pin #  
Name  
Description  
44  
48  
PLCC SSOP  
1
48  
6
CSTo  
Control ST-BUS Output (Output). This is a 2.048 Mb/s output containing 256 bits per  
frame. The level of each bit is determined by the CSTo bit in the Connect Memory high  
locations.  
6
AS/ALE Address Strobe or Latch Enable (5 V tolerant Input). This input is only used if  
multiplexed bus is selected via the IM input pin.  
The falling edge of this signal is used to sample the address into the address latch  
circuit. When the non-multiplexed bus interface is selected, this input is not required  
and should be connected to ground.  
18  
28  
19  
30  
IM  
CPU Interface Mode (5 V tolerant Input). If HIGH, this input configures the MT89L86  
in the multiplexed microprocessor bus mode. When this input pin is connected to  
ground, the MT89L86 assumes non-multiplexed CPU interface.  
STi15/ ST-BUS Input 15 / ST-BUS Output 9 (Input/three-state output). This pin is only used  
STo9  
if multiplexed CPU bus is selected. If 16-input x 8-output switching configuration is  
enabled in the SCB bits (IMS register), this pin is an input receiving serial ST-BUS  
stream 15 at a data rate of 2.048 Mbit/s.  
If Stream Pair Selection capability is enabled (see switching configuration section), this  
pin is the ST-BUS stream 9 output.  
When non-multiplexed bus structure is used, this pin should be connected to ground.  
40  
43  
STi14/ ST-BUS Input 14 / ST-BUS Output 8 (Input/three-state output). This pin is only used  
STo8  
if multiplexed CPU bus is selected. If 16-input x 8-output switching configuration is  
enabled in the SCB bits (IMS register), this pin is an input that receives serial ST-BUS  
stream 14 at a data rate of 2.048 Mbit/s.  
If Stream Pair Selection capability is enabled (see switching configuration section), this  
pin is the ST-BUS stream 8 output.  
When non-multiplexed bus structure is used, this pin should be connected to ground.  
Device Overview  
With the integration of voice, video and data services in the same network, there has been an increasing demand  
for systems which ensure that data at N x 64 kb/s rates maintain sequence integrity while being transported through  
time-slot interchange circuits. This requirement demands time-slot interchange devices which perform switching  
with constant throughput delay for wideband data applications while maintaining minimum delay for voice channels.  
The MT89L86 device meets the above requirement and allows existing systems based on the MT8980D to be  
easily upgraded to maintain the data integrity when wideband data is transported. The device is designed to switch  
32, 64 or N x 64 bit/s data. This MT89L86 can provide frame integrity for data applications and minimum throughput  
switching delay for voice applications on a per channel basis.  
The serial streams of the MT89L86 can operate at 2.048, 4.096 or 8.192 Mbit/s and are arranged in 125 s wide  
frames which contain 32, 64 and 128 channels, respectively. In addition, a built-in rate conversion circuit allows the  
user to interconnect various backbone speeds like 2.048 or 4.096 or 8.192 Mb/s while maintaining the control of  
throughput delay function on a per-channel basis.  
By using Zarlink Message mode capability, the microprocessor can access input and output time-slots on a per  
channel basis to control external circuits or other ST-BUS devices. This MT89L86 automatically identifies the  
polarity of the frame synchronization input signal and configures its serial port to be compatible to both ST-BUS and  
GCI formats.  
5
Zarlink Semiconductor Inc.  
12345678...44

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