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MT89L86AN1 PDF预览

MT89L86AN1

更新时间: 2024-01-11 18:08:16
品牌 Logo 应用领域
美高森美 - MICROSEMI 电信光电二极管电信集成电路
页数 文件大小 规格书
44页 432K
描述
Digital Time Switch, CMOS, PDSO48, 0.300 INCH, LEAD FREE, MO-118AA, SSOP-48

MT89L86AN1 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:SSOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.65
JESD-30 代码:R-PDSO-G48JESD-609代码:e3
长度:15.88 mm湿度敏感等级:3
功能数量:1端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:2.79 mm标称供电电压:3.3 V
表面贴装:YES技术:CMOS
电信集成电路类型:DIGITAL TIME SWITCH温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.64 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.49 mm
Base Number Matches:1

MT89L86AN1 数据手册

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MT89L86  
Data Sheet  
Pin Description (continued)  
Pin #  
Name  
Description  
44  
48  
PLCC SSOP  
22  
23  
24  
23  
24  
26  
DS/RD Data Strobe/Read (5 V tolerant Input). When the non-multiplexed CPU bus or  
Motorola multiplexed bus is selected, this input is DS. This active high input works in  
conjunction with CS to enable read and write operation.  
For the Intel/National multiplexed bus interface, this input is RD. This active low input  
configures the data bus lines (AD0-7) as outputs.  
R/W\WR Read/Write \ Write (5 V tolerant Input). For the non-multiplexed or Motorola  
multiplexed bus interface, this input is R/W. This input controls the direction of the data  
bus lines (AD0-AD7) during a microprocessor access.  
For the Intel/National multiplexed bus interface, this input is WR. This active low signal  
configures the data bus lines (AD0-7) as inputs.  
CS  
Chip Select (5 V tolerant Input). This active low input enables a microprocessor read  
or write of the MT89L86’s internal control register or memories.  
25-27 27-29 AD7-AD0 Data Bus (Bidirectional): These pins provide microprocessor access to the internal  
29-33 31-35  
control registers, connection memories high and low and data memories. For the  
multiplexed bus interface these pins also provide the input address to the internal  
Address Latch circuit.  
34  
35  
1,  
25,37  
VSS  
Ground.  
38  
STo7/A7 ST-BUS Output 7/Address 7 input (Three-state output/input). The function of this pin  
is determined by the switching configuration enabled. If non-multiplexed CPU bus is  
used along with data rates employing 8.192 Mb/s rates, this pin provides A7 address  
input function. For 2.048 Mb/s applications or when the multiplexed CPU bus interface  
is selected, this pin assumes STo7 function. See Tables 1, 2, 6 & 7 for more details.  
Note that for applications where A7 input and STo7 output are required simultaneously  
(e.g., 8.192 to 2.048 Mb/s rate conversion), the A7 input should be connected to pin  
STi7/A7.  
36  
39  
STo6/A6 ST-BUS Output 6/Address 6 input (Three-state output/input). The function of this  
pin is determined by the switching configuration enabled. If non-multiplexed CPU bus  
is used along with a higher data rate employing 8.192 or 4.096 Mb/s, this pin provides  
the A6 address input function. For 2.048 Mb/s applications or when the multiplexed  
CPU bus interface is selected, this pin assumes STo6 function. See Tables 1, 2, 6 & 7  
for more details.  
Note that for applications where both A6 input and STo6 output are required  
simultaneously (e.g., 4.096 to 2.048 Mb/s or 8.192 to 2.048 Mb/s rate conversion  
applications), the A6 input should be connected to pin STi6/A6.  
37-39 40-42 STo5-0 ST-BUS Outputs 5 to 0 (Three-state Outputs). Serial data output streams. These  
41-43 44-46  
serial streams may be composed of 32, 64 and 128 channels at data rates of 2.048,  
4.096 or 8.192 Mbit/s, respectively.  
44 47  
ODE  
Output Drive Enable (5 V tolerant Input). This is the output enable input for the STo0  
to STo9 serial outputs. If this input is low STo0-9 are high impedance. If this input is  
high each channel may still be set to high impedance by using per-channel control bits  
in Connect Memory High.  
4
Zarlink Semiconductor Inc.  

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