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MT8931C

更新时间： 2024-02-25 11:16:53
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 网络接口
页数 文件大小 规格书
39页 836K
描述
Subscriber Network Interface Circuit

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MT8931C 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：LPCC
包装说明：QCCJ,针数：44
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.76JESD-30 代码：S-PQCC-J44
JESD-609代码：e0长度：16.585 mm
湿度敏感等级：1功能数量：1
端子数量：44最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：225
认证状态：Not Qualified座面最大高度：4.57 mm
标称供电电压：5 V表面贴装：YES
技术：CMOS电信集成电路类型：DIGITAL SLIC
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：16.585 mmBase Number Matches：1

MT8931C 数据手册

 浏览型号MT8931C的Datasheet PDF文件第1页浏览型号MT8931C的Datasheet PDF文件第3页浏览型号MT8931C的Datasheet PDF文件第4页浏览型号MT8931C的Datasheet PDF文件第5页浏览型号MT8931C的Datasheet PDF文件第6页浏览型号MT8931C的Datasheet PDF文件第7页 
MT8931C  
Data Sheet  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
1
2
HALF  
C4b  
VDD  
VBias  
LTx  
F0b  
3
4
5
40  
44 43 42 41  
6 5 4 3 2  
1
F0od  
LRx  
NC  
7
F0od  
DSTi  
DSTo  
39  
DSTi  
STAR/Rsto  
Rsti  
8
STAR/Rsto  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
DSTo  
9
6
7
Rsti  
NC  
10  
11  
12  
13  
14  
15  
16  
XTAL2/NC  
XTAL1/NT  
R/W/WR  
DS/RD  
AS/ALE  
CS  
AD7  
NC  
NC  
AD7  
AD6  
NC  
8
AD6  
NC  
AD5  
9
XTAL2/NC  
AD4  
10  
11  
12  
13  
14  
AD5  
AD4  
AD3  
NC  
XTAL1/NT  
NC  
AD3  
AD2  
R/W/WR  
IRQ/NDA  
VSS  
AD1  
DS/RD  
17  
AD0  
181920 21 22 23 24 25 26 27 28  
28 PIN PDIP  
44 PIN PLCC  
Figure 2 - Pin Connections  
Pin Description  
Pin #  
DIP PLCC  
Name  
Description  
1
2
HALF  
HALF Input/Output: this is an input in NT mode and an output in TE mode identifying  
which half of the S-interface frame is currently being written/read over the ST-BUS  
(HALF = 0 sampled on the falling edge of C4b within the frame pulse low window,  
identifies the information to be transmitted/received in the first half of the S-Bus frame  
while HALF=1 identifies the information to be transmitted/received into the second half  
of the S-Bus frame). Tying this pin to VSS or VDD in NT mode will allow the device to free  
run. This signal can also be accessed from the ST-BUS C-channel.  
2
3
4
3
4
7
C4b  
F0b  
4.096 MHz Clock: a 4.096 MHz ST-BUS Data Clock input in NT mode.  
In TE mode an output 4.096 MHz clock phase-locked to the line data signal.  
Frame Pulse: an active low frame pulse input indicating the beginning of active ST-  
BUS channel times in NT mode. Frame pulse output in TE mode.  
F0od  
Delayed Frame Pulse Output: an active low delayed frame pulse output indicating  
the end of active ST-BUS channels for this device. Can be used to daisy chain  
to other ST-BUS devices to share an ST-BUS stream.  
5
6
8
9
DSTi  
Data ST-BUS Input: a 2048 kbit/s serial PCM/data ST-BUS input with D, C, B1, and B2  
channels assigned to the first four timeslots. These channels contain data to be  
transmitted on the line and chip control information.  
Data ST-BUS Output: a 2048 kbit/s serial PCM/data ST-BUS output with D, C, B1 and  
B2 channels assigned to the first four timeslots, respectively. The remaining timeslots  
are placed into high impedance. These channels contain data received from the line  
and chip status information.  
DSTo  
7
8
13  
14  
XTAL2/IC Crystal 2/Internal Connection: in TE mode, XTAL1 and XTAL2 are to be connected to  
an external 4.096 MHz parallel resonant crystal for the on-chip oscillator.  
If XTAL1 is connected directly to a 4.096 MHz clock, this pin must be left unconnected.  
In NT mode, this pin must be left unconnected.  
XTAL1/NT Crystal 1/Network Termination Mode Select Input: for TE mode mode selection, a  
4.096 MHz crystal is to be connected between the XTAL1 and XTAL2 pins, or a 4.096  
MHz clock can be connected directly to XTAL1. For NT mode selection, this pin must  
be tied to VDD. A pull-up resistor is needed when driven by a TTL device.  
2
1234567...39

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