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MT5C6401C-25L/IT PDF预览

MT5C6401C-25L/IT

更新时间: 2024-01-28 14:13:05
品牌 Logo 应用领域
AUSTIN 存储内存集成电路静态存储器
页数 文件大小 规格书
10页 133K
描述
64K x 1 SRAM SRAM MEMORY ARRAY

MT5C6401C-25L/IT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP22,.3Reach Compliance Code:not_compliant
风险等级:5.92最长访问时间:25 ns
I/O 类型:SEPARATEJESD-30 代码:R-XDIP-T22
JESD-609代码:e0内存密度:65536 bit
内存集成电路类型:STANDARD SRAM内存宽度:1
端子数量:22字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:64KX1输出特性:3-STATE
封装主体材料:CERAMIC封装代码:DIP
封装等效代码:DIP22,.3封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:PARALLEL
电源:5 V认证状态:Not Qualified
最大待机电流:0.00025 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.12 mA
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
Base Number Matches:1

MT5C6401C-25L/IT 数据手册

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SRAM  
MT5C6401  
Austin Semiconductor, Inc.  
64K x 1 SRAM  
PIN ASSIGNMENT  
SRAM MEMORY ARRAY  
(Top View)  
22-Pin DIP (C)  
(300 MIL)  
AVAILABLE AS MILITARY  
SPECIFICATIONS  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
Q
1
2
3
4
5
6
7
8
9
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
Vcc  
A15  
A14  
A13  
A12  
A11  
A10  
A9  
SMD 5962-86015  
MIL-STD-883  
A8  
FEATURES  
WE\ 10  
Vss 11  
D
CE\  
• Speeds: 12, 15, 20, 25, 35, 45, 55, and 70ns  
• Battery Backup: 2V data retention  
• High-performance, low-power CMOS double-metal  
process  
• Single +5V (+10%) Power Supply  
• Easy memory expansion with CE\  
• All inputs and outputs are TTL compatible  
GENERAL DESCRIPTION  
The Austin Semiconductor SRAM family employs  
high-speed, low-power CMOS designs using a four-transistor  
memory cell. Austin Semiconductor SRAMs are fabricated  
using double-layer metal, double-layer polysilicon  
technology.  
For flexibility in high-speed memory applications, Austin  
Semiconductor offers chip enable (CE\) on all organizations.  
This enhancement can place the outputs in High-Z for  
additional flexibility in system design. The X1 configuration  
features separate data input and output.  
Writing to these devices is accomplished when write  
enable (WE\) and CE\ inputs are both LOW. Reading is  
accomplished when WE\ remains HIGH and CE\ goes LOW.  
The device offers a reduced power standby mode when  
disabled. This allows system designs to achieve low standby  
power requirements.  
OPTIONS  
• Timing  
MARKING  
12ns access  
15ns access  
20ns access  
25ns access  
35ns access  
45ns access  
55ns access  
70ns access  
-12  
-15  
-20  
-25  
-35  
-45*  
-55*  
-70*  
• Package(s)  
Ceramic DIP (300 mil)  
C
No. 105  
All devices operate from a single +5V power supply and  
all inputs and outputs are fully TTL compatible.  
• Operating Temperature Ranges  
Industrial (-40oC to +85oC)  
Military (-55oC to +125oC)  
IT  
XT  
• 2V data retention/low power  
L
For more products and information  
please visit our web site at  
*Electrical characteristics identical to those provided for the 35ns  
access devices.  
www.austinsemiconductor.com  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
MT5C6401  
Rev. 1.0 8/01  
1

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