SRAM
MT5C1001
Limited Availability
Austin Semiconductor, Inc.
1M x 1 SRAM
PIN ASSIGNMENT
(Top View)
SRAM MEMORY ARRAY
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
AVAILABLE AS MILITARY
28-Pin DIP (C)
(400 MIL)
SPECIFICATIONS
• SMD 5962-92316
• MIL-STD-883
A10
A11
A12
NC
A13
A14
A15
NC
A16
A17
A18
A19
NC
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
NC
A9
A8
A7
A6
A5
A4
A3
NC
A2
NC
A1
A0
D
A10
A11
A12
A13
A14
A15
NC
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
A9
A8
A7
A6
A5
A4
NC
A3
A2
A1
A0
D
FEATURES
• High Speed: 20, 25, 35, and 45
• Battery Backup: 2V data retention
• Low power standby
9
A16
A17
10
11
12
13
14
15
16
A18 10
A19 11
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\ and OE\ options.
• All inputs and outputs are TTL compatible
• Three-state output
Q
12
Q
WE\
Vss
WE\ 13
Vss 14
CE\
CE\
32-Pin Flat Pack (F)
OPTIONS
• Timing
MARKING
1
A10
Vcc
NC
A9
A8
A7
A6
A5
A4
A3
NC
A2
NC
A1
A0
D
3 2
2
A11
A12
NC
A13
A14
A15
NC
A16
A17
A18
A19
NC
3 1
3
3 0
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
-20
4
2 9
5
2 8
-25
-35
-45
-55*
-70*
6
2 7
7
2 6
8
2 5
9
2 4
1 0
1 1
1 2
1 3
1 4
1 5
1 6
2 3
2 2
2 1
2 0
1 9
1 8
1 7
Q
WE\
Vss
• Package(s)
CE\
Ceramic DIP (400 mil)
CeramicLCC
Ceramic Flatpack
Ceramic SOJ
C
EC
F
No. 109
No. 207
No. 303
No. 501
GENERAL DESCRIPTION
DCJ
The MT5C1001 employs low power, high-performance
silicon-gate CMOS technology. Static design eliminates the
need for external clocks or timing strobes while CMOS circuitry
reduces power consumption and provides for greater
reliability.
• Operating Temperature Ranges
Industrial (-40oC to +85oC)
Military (-55oC to +125oC)
IT
XT
For flexibility in high-speed memory applications, ASI
offers chip enable (CE\) and output enable (OE\) capability.
These enhancements can place the outputs in High-Z for addi-
tional flexibility in system design. Writing to these devices is
accomplished when write enable (WE|) and CE\ inputs are both
LOW. Reading is accomplished when WE\ remains HIGH while
CE\ and OE\ go LOW. The devices offer a reduced power
standby mode when disabled. This allows system designs to
achieve low standby power requirements.
• 2V data retention/low power
L
*Electrical characteristics identical to those provided for the
45ns access devices.
For more products and information
please visit our web site at
The “L” version provides an approximate 50 percent
www.austinsemiconductor.com
reduction in CMOS standby current (ISBC2) over the standard
version.
All devices operation from a single +5V power supply
and all inputs and outputs are fully TTL compatible.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C1001
Rev. 2.0 2/00
1