Datasheet > MT5C1001DCJ-45/883C

MT5C1001DCJ-45/883C

更新时间： 2024-11-08 05:50:35

品牌	Logo	应用领域
AUSTIN		存储静态存储器
页数	文件大小	规格书
13页	95K
描述
1M x 1 SRAM SRAM MEMORY ARRAY

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SRAM

MT5C1001

Limited Availability

Austin Semiconductor, Inc.

1M x 1 SRAM

SRAM MEMORY ARRAY

PIN ASSIGNMENT

(Top View)

32-Pin LCC (EC)

32-Pin SOJ (DCJ)

AVAILABLE AS MILITARY

28-Pin DIP (C)

(400 MIL)

SPECIFICATIONS

• SMD 5962-92316

• MIL-STD-883

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

Vcc

A10

A11

A12

A13

A14

A15

Vcc

FEATURES

• High Speed: 20, 25, 35, and 45

• Battery Backup: 2V data retention

• Low power standby

• Single +5V (+10%) Power Supply

• Easy memory expansion with CE\ and OE\ options.

• All inputs and outputs are TTL compatible

• Three-state output

A16

A17

A18 10

A19 11

WE\

Vss

WE\ 13

Vss 14

CE\

32-Pin Flat Pack (F)

OPTIONS

• Timing

MARKING

A10

Vcc

3 2

A11

A12

A13

A14

A15

A16

A17

A18

A19

3 1

3 0

20ns access

25ns access

35ns access

45ns access

55ns access

70ns access

-20

2 9

2 8

-25

-35

-45

-55*

-70*

2 7

2 6

2 5

2 4

1 0

1 1

1 2

1 3

1 4

1 5

1 6

2 3

2 2

2 1

2 0

1 9

1 8

1 7

WE\

Vss

• Package(s)

CE\

Ceramic DIP (400 mil)

CeramicLCC

Ceramic Flatpack

Ceramic SOJ

No. 109

No. 207

No. 303

No. 501

GENERAL DESCRIPTION

DCJ

The MT5C1001 employs low power, high-performance

silicon-gate CMOS technology. Static design eliminates the

need for external clocks or timing strobes while CMOS circuitry

reduces power consumption and provides for greater

reliability.

• OperatingTemperature Ranges

Industrial (-40^oC to +85^oC)

Military (-55^oC to +125^oC)

For flexibility in high-speed memory applications, ASI

offers chip enable (CE\) and output enable (OE\) capability.

These enhancements can place the outputs in High-Z for addi-

tional flexibility in system design. Writing to these devices is

accomplished when write enable (WE|) and CE\ inputs are both

LOW. Reading is accomplished when WE\ remains HIGH while

CE\ and OE\ go LOW. The devices offer a reduced power

standby mode when disabled. This allows system designs to

achieve low standby power requirements.

• 2V data retention/low power

*Electrical characteristics identical to those provided for the

45ns access devices.

For more products and information

please visit our web site at

The “L” version provides an approximate 50 percent

www.austinsemiconductor.com

reduction in CMOS standby current (I_SBC2) over the standard

version.

All devices operation from a single +5V power supply

and all inputs and outputs are fully TTL compatible.

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

MT5C1001

Rev. 2.1 06/05

12 3 4 5 6 7...13

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与MT5C1001DCJ-45/883C相关器件

型号	品牌	获取价格	描述	数据表
MT5C1001DCJ-45/IT	MICROSS	获取价格	Standard SRAM, 1MX1, 45ns, CMOS, CDSO32, CERAMIC, SOJ-32
MT5C1001DCJ-45/XT	MICROSS	获取价格	Standard SRAM, 1MX1, 45ns, CMOS, CDSO32, CERAMIC, SOJ-32
MT5C1001DCJ-45E/883C	MICROSS	获取价格	Standard SRAM, 1MX1, 45ns, CMOS, CDSO32, CERAMIC, SOJ-32
MT5C1001DCJ-45L/883C	AUSTIN	获取价格	1M x 1 SRAM SRAM MEMORY ARRAY
MT5C1001DCJ-45L/883C	MICROSS	获取价格	Standard SRAM, 1MX1, 45ns, CMOS, CDSO32, CERAMIC, SOJ-32
MT5C1001DCJ-45L/XT	MICROSS	获取价格	Standard SRAM, 1MX1, 45ns, CMOS, CDSO32, CERAMIC, SOJ-32
MT5C1001DCJ-45LE/883C	MICROSS	获取价格	Standard SRAM, 1MX1, 45ns, CMOS, CDSO32, CERAMIC, SOJ-32
MT5C1001DCJ-45P/883C	MICROSS	获取价格	Standard SRAM, 1MX1, 45ns, CMOS, CDSO32, CERAMIC, SOJ-32
MT5C1001DCJ-55/883C	AUSTIN	获取价格	1M x 1 SRAM SRAM MEMORY ARRAY
MT5C1001DCJ-55/883C	MICROSS	获取价格	Standard SRAM, 1MX1, 55ns, CMOS, CDSO32, CERAMIC, SOJ-32

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