Datasheet > MT58L64L36PT-7.5T

MT58L64L36PT-7.5T

更新时间： 2024-11-08 05:35:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
17页	306K
描述
Standard SRAM, 64KX36, 4ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

MT58L64L36PT-7.5T 数据手册

浏览型号MT58L64L36PT-7.5T的Datasheet PDF文件第2页

浏览型号MT58L64L36PT-7.5T的Datasheet PDF文件第3页

浏览型号MT58L64L36PT-7.5T的Datasheet PDF文件第4页

浏览型号MT58L64L36PT-7.5T的Datasheet PDF文件第5页

浏览型号MT58L64L36PT-7.5T的Datasheet PDF文件第6页

浏览型号MT58L64L36PT-7.5T的Datasheet PDF文件第7页

2Mb: 128K x 18, 64K x 32/36

PIPELINED, SCD SYNCBURST SRAM

MT58L128L18P, MT58L64L32P, MT58L64L36P;

MT58L128V18P, MT58L64V32P, MT58L64V36P

2Mb SYNCBURST^™

SRAM

3.3V VDD, 3.3V or 2.5V I/O, Pipelined, Single-Cycle

Deselect

FEATURES

• Fast clock and OE# access times

• Single +3.3V +0.3V/-0.165V power supply (V^DD)

• Separate +3.3V or +2.5V isolated output buffer supply

(VDDQ)

100-Pin TQFP**

(D-1)

• SNOOZE MODE for reduced-power standby

• Single-cycle deselect (Pentium BSRAM-compatible)

• Common data inputs and data outputs

• Individual BYTE WRITE control and GLOBAL WRITE

• Three chip enables for simple depth expansion and

address pipelining

• Clock-controlled and registered addresses, data I/Os

and control signals

• Internally self-timed WRITE cycle

• Burst control pin (interleaved or linear burst)

• Automatic power-down for portable applications

• 100-lead TQFP for high density, high speed

• Low capacitive bus loading

**JEDEC-standard MS-026 BHA (LQFP).

• x18, x32 and x36 options available

GENERAL DESCRIPTION

OPTIONS

MARKING

™

The Micron SyncBurst SRAM family employs high-

speed, low-power CMOS designs that are fabricated using

an advanced CMOS process.

• Timing (Access/Cycle/MHz)

3.5ns/5ns/200 MHz

3.5ns/6ns/166 MHz

4.2ns/7.5ns/133 MHz

5ns/10ns/100 MHz

-5

-6

-7.5

-10

Micron’s 2Mb SyncBurst SRAMs integrate a 128K x 18,

64Kx32,or64Kx36SRAMcorewithadvancedsynchronous

peripheral circuitry and a 2-bit burst counter. All

synchronous inputs pass through registers controlled by a

positive-edge-triggered single clock input (CLK). The

synchronous inputs include all addresses, all data inputs,

active LOW chip enable (CE#), two additional chip enables

for easy depth expansion (CE2, CE2#), burst control inputs

(ADSC#, ADSP#, ADV#), byte write enables (BWx#) and

global write (GW#).

Asynchronous inputs include the output enable (OE#),

clock (CLK) and snooze enable (ZZ). There is also a burst

mode pin (MODE) that selects between interleaved and

linear burst modes. The data-out (Q), enabled by OE#, is

also asynchronous. WRITE cycles can be from one to two

bytes wide (x18) or from one to four bytes wide (x32/x36),

as controlled by the write control inputs.

• Configurations

3.3V I/O

128K x 18

64K x 32

64K x 36

MT58L128L18P

MT58L64L32P

MT58L64L36P

2.5V I/O

128K x 18

64K x 32

64K x 36

MT58L128V18P

MT58L64V32P

MT58L64V36P

• Package

100-pin TQFP

• Operating Temperature Range

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

Burstoperationcanbeinitiatedwitheitheraddressstatus

processor (ADSP#) or address status controller (ADSC#)

input pins. Subsequent burst addresses can be internally

generated as controlled by the burst advance pin (ADV#).

Address and write control are registered on-chip to

simplifyWRITEcycles.Thisallowsself-timedWRITEcycles.

None

• Part Number Example: MT58L128L18PT-10 T

*Under consideration.

2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM

MT58L128L18P.p65 – Rev. 7/99

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1999, Micron Technology, Inc.

All registered and unregistered trademarks are the sole property of their respective companies.

12 3 4 5 6 7...17

中文翻译

下载PDF

与MT58L64L36PT-7.5T相关器件

型号	品牌	获取价格	描述	数据表
MT58L64V32F	MICRON	获取价格	2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM
MT58L64V32FF-10	CYPRESS	获取价格	Standard SRAM, 64KX32, 10ns, CMOS, PBGA165, FBGA-165
MT58L64V32FF-6.8	CYPRESS	获取价格	Standard SRAM, 64KX32, 6.8ns, CMOS, PBGA165, FBGA-165
MT58L64V32FF8.5	CYPRESS	获取价格	64KX32 STANDARD SRAM, 8.5ns, PBGA165, FBGA-165
MT58L64V32FT-10	MICRON	获取价格	2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM
MT58L64V32FT-10IT	CYPRESS	获取价格	Standard SRAM, 64KX32, 10ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L64V32FT-10T	CYPRESS	获取价格	Cache SRAM, 64KX32, 10ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100
MT58L64V32FT-6.8	MICRON	获取价格	2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM
MT58L64V32FT-6.8IT	CYPRESS	获取价格	Cache SRAM, 64KX32, 6.8ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L64V32FT-6.8T	CYPRESS	获取价格	Cache SRAM, 64KX32, 6.8ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100

与MT58L64L36PT-7.5T相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

19
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

16
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

39
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

37

产品中心

服务支持

精选活动

关于我们

帮助中心

MT58L64L36PT-7.5T

MT58L64L36PT-7.5T 数据手册

与MT58L64L36PT-7.5T相关器件

与MT58L64L36PT-7.5T相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MT58L64L36PT-7.5T

MT58L64L36PT-7.5T 数据手册

与MT58L64L36PT-7.5T相关器件

与MT58L64L36PT-7.5T相关文章

您还可以找

您在本页遇到什么问题？