Datasheet > MT58L128L18PT-7.5T

MT58L128L18PT-7.5T

更新时间： 2023-02-15 00:00:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
17页	306K
描述
Standard SRAM, 128KX18, 4ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100

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数据手册

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2Mb: 128K x 18, 64K x 32/36

PIPELINED, SCD SYNCBURST SRAM

PIN ASSIGNMENT (Top View)

100-Pin TQFP

(D-1)

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

ADV#

ADSP#

ADSC#

OE#

BWE#

GW#

CLK

NC/SA*

DNU

x18

CE2#

BWa#

BWb#

DNU

SA0

SA1

CE2

CE#

100

MODE

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

ADV#

ADSP#

ADSC#

OE#

BWE#

GW#

CLK

NC/SA*

DNU

VSS

x32/x36

CE2#

BWa#

BWb#

BWc#

BWd#

CE2

DNU

SA0

SA1

CE#

100

MODE

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

Pin 50 is reserved for address expansion.

** No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.

2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM

MT58L128L18P.p65 – Rev. 7/99

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1999, Micron Technology, Inc.

1 2 345 6 7...17

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