Datasheet > MT57V256H36PF-5

MT57V256H36PF-5

更新时间： 2024-02-09 10:22:12

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		双倍数据速率静态存储器内存集成电路
页数	文件大小	规格书
23页	388K
描述
DDR SRAM, 256KX36, 2.4ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165

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MT57V256H36PF-5 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
零件包装代码：	BGA	包装说明：	13 X 15 MM, FBGA-165
针数：	165	Reach Compliance Code：	not_compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.61	最长访问时间：	2.4 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	200 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e0	长度：	15 mm
内存密度：	9437184 bit	内存集成电路类型：	DDR SRAM
内存宽度：	36	功能数量：	1
端子数量：	165	字数：	262144 words
字数代码：	256000	工作模式：	SYNCHRONOUS
组织：	256KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, THIN PROFILE	并行/串行：	PARALLEL
电源：	1.5,2.5 V	认证状态：	Not Qualified
座面最大高度：	1.2 mm	最大待机电流：	0.075 A
最小待机电流：	2.4 V	子类别：	SRAMs
最大压摆率：	0.35 mA	最大供电电压 (Vsup)：	2.6 V
最小供电电压 (Vsup)：	2.4 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
宽度：	13 mm	Base Number Matches：	1

MT57V256H36PF-5 数据手册

256K x 36

2.5V VDD, HSTL, PIPELINED DDR SRAM

MT57V256H36P

9Mb

DDR SRAM

FEATURES

• Fast cycle times: 5ns and 6ns

165-Ball FBGA

• 256K x 36 configuration

• Pipelined double data rate operation

• Single +2.5V ±0.1V power supply (V^DD)

• Separate isolated output buffer supply (V^DDQ)

• JEDEC-standard HSTL I/O

• User-selectable trip point with VREF

• HSTL programmable impedance outputs synchro-

nized to optional dual data clocks

• Echo clock outputs

• JTAG boundary scan

• Fully static design for reduced-power standby

• Clock-stop capability

• Common data inputs and data outputs

• Low control ball count

• Internally self-timed, registered LATE WRITE cycle

• Linear burst order with four-tick burst counter

• 13 x 15mm, 1mm pitch, 11 x 15 grid FBGA package

• Full data coherency, providing most current data

OPTIONS

MARKING*

latched on the rising edge of K and K#. The synchronous

inputs include all addresses, all data inputs, active LOW

load (LD#) and read/write (R/W#). Write data is regis-

tered on the rising edges of both K and K#. Read data is

driven on the rising edge of C and C# if provided, or on the

rising edge of K and K# if C and C# are not provided.

Asynchronousinputsincludeimpedancematch(ZQ).

Synchronous data outputs (Q) are closely matched to the

two echo clocks (CQ and CQ#), which can be used as data

receive clocks. Output data clocks (C, C#) are also pro-

vided for maximum system clocking and data synchroni-

zation flexibility.

Additionalwriteregistersareincorporatedtoenhance

pipelinedWRITEcyclesandreduceREAD-to-WRITEturn-

around time. WRITE cycles are self-timed.

Thedevicedoesnotutilizeinternalphase-lockedloops

and can therefore be placed into a stopped-clock state to

minimize power without lengthy restart times.

• Clock Cycle Timing

5ns (200 MHz)

6ns (167 MHz)

-5

-6

• Configuration

256K x 36

MT57V256H36P

• Package

165-ball, 13mm x 15mm FBGA

* A Part Marking Guide for the FBGA devices can be found on Micron’s

Web site—http://www.micron.com/numberguide.

VALID PART NUMBERS

PART NUMBER

MT57V256H36PF-xx

DESCRIPTION

256K x 36, HSTL, DDR, Pipelined

GENERAL DESCRIPTION

Four balls are used to implement JTAG test capabili-

ties: test mode select (TMS), test data-in (TDI), test clock

(TCK) and test data-out (TDO). JTAG circuitry is used to

serially shift data to and from the SRAM. JTAG inputs use

JEDEC-standard 2.5V I/O levels to shift data during this

testing mode of operation.

TheMicron®DDRSynchronousSRAMemployshigh-

speed, low-power CMOS designs using an advanced 6T

CMOS process.

The DDR SRAM integrates a 9Mb SRAM core with

advanced synchronous peripheral circuitry and a 2-bit

burst counter. All synchronous inputs pass through reg-

isters controlled by an input clock pair (K and K#) and are

The device can be used in HSTL systems by supplying

an appropriate reference voltage (VREF). The device is

256K x 36 2.5V VDD, HSTL, Pipelined DDR SRAM

MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

12 3 4 5 6 7...23

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与MT57V256H36PF-5相关器件

型号	品牌	获取价格	描述	数据表
MT57V256H36PF-6	CYPRESS	获取价格	DDR SRAM, 256KX36, 3ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165
MT57V512H36AF-6	CYPRESS	获取价格	DDR SRAM, 512KX36, 3ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
MT57V512H36AF-7.5	CYPRESS	获取价格	DDR SRAM, 512KX36, 3.6ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
MT57V512H36AF-7.5	ROCHESTER	获取价格	512KX36 DDR SRAM, 3.6ns, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
MT57V512H36EF-5	CYPRESS	获取价格	DDR SRAM, 512KX36, 2.4ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
MT57V512H36EF-5	ROCHESTER	获取价格	512KX36 DDR SRAM, 2.4ns, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
MT57V512H36EF-6	CYPRESS	获取价格	DDR SRAM, 512KX36, 3ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
MT57V512H36EF-7.5	CYPRESS	获取价格	DDR SRAM, 512KX36, 3.6ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
MT57W1MH18BF-3	CYPRESS	获取价格	DDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
MT57W1MH18BF-3.3	CYPRESS	获取价格	DDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165

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