Datasheet > MT54V512H36AF-10

MT54V512H36AF-10

更新时间： 2024-11-09 19:11:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器内存集成电路
页数	文件大小	规格书
25页	375K
描述
QDR SRAM, 512KX36, 3ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165

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中文翻译

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技术参数
数据手册

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MT54V512H36AF-10 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	TBGA,	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.69
最长访问时间：	3 ns	其他特性：	PIPELINED ARCHITECTURE
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e0
长度：	15 mm	内存密度：	18874368 bit
内存集成电路类型：	QDR SRAM	内存宽度：	36
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	524288 words
字数代码：	512000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	512KX36	封装主体材料：	PLASTIC/EPOXY
封装代码：	TBGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, THIN PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	220	认证状态：	Not Qualified
座面最大高度：	1.2 mm	最大供电电压 (Vsup)：	2.6 V
最小供电电压 (Vsup)：	2.4 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN LEAD
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	13 mm	Base Number Matches：	1

MT54V512H36AF-10 数据手册

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, QDRb2 SRAM

MT54V1MH18A

MT54V512H36A

18Mb QDR^™SRAM

2-WORD BURST

Features

Figure 1: 165-Ball FBGA

•

Separate independent read and write data ports

with concurrent transactions

100 percent bus utilization DDR READ and WRITE

operation

High frequency operation with future migration to

higher clock frequencies

•

Fast clock to valid data times

Full data coherency, providing most current data

Two-tick burst counter for low DDR transaction size

Double data rate operation on read and write ports

Two input clocks (K and K#) for precise DDR timing

at clock rising edges only

•

Two output clocks (C and C#) for precise flight time

and clock skew matching—clock and data delivered

together to receiving device

Optional-use echo clocks (CQ and CQ#) for flexible

receive data synchronization

Table 1:

Valid Part Numbers

PART NUMBER

DESCRIPTION

•

Single address bus

Simple control logic for easy depth expansion

Internally self-timed, registered writes

2.5V core and 1.5 to 1.8V ( 0.1V) HSTL I/O

Clock-stop capability

13mm x 15mm, 1mm pitch, 11 x 15 grid FBGA

package

MT54V1MH18AF-xx

MT54V512H36AF-xx

1 Meg x 18, QDRb2 FBGA

512K x 36, QDRb2 FBGA

General Description

The Micron^®QDR™ (Quad Data Rate™) synchro-

nous, pipelined burst SRAM employs high-speed, low-

power CMOS designs using an advanced 6T CMOS

process.

•

User-programmable impedance output

JTAG boundary scan

The QDR architecture consists of two separate DDR

(double data rate) ports to access the memory array.

The read port has dedicated data outputs to support

READ operations. The write port has dedicated data

inputs to support WRITE operations. This architecture

eliminates the need for high-speed bus turnaround.

Access to each port is accomplished using a common

address bus. Addresses for reads and writes are latched

on rising edges of the K and K# input clocks, respec-

tively. Each address location is associated with two

words that burst sequentially into or out of the device.

Since data can be transferred into and out of the device

on every rising edge of both clocks (K and K# and C

and C#), memory bandwidth is maximized and system

design is simplified by eliminating bus turnarounds.

Options

Marking¹

•

Clock Cycle Timing

6ns (167 MHz)

-6

-7.5

-10

7.5ns (133 MHz)

10ns (100 MHz)

•

Configurations

1 Meg x 18

512K x 36

MT54V1MH18A

MT54V512H36A

•

Package

165-ball, 13mm x 15mm FBGA

Operating Temperature Range

Commercial (0°C ? T_A? +70°C)

None

NOTE:

1. A Part Marking Guide for the FBGA devices can be found on

Micron’s Web site—http://www.micron.com/numberguide.

18Mb: 2.5V VDD, HSTL, QDRb2 SRAM

MT54V1MH18A_16_F.fm – Rev. F, Pub. 3/03

12 3 4 5 6 7...25

中文翻译

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与MT54V512H36AF-10相关器件

型号	品牌	获取价格	描述	数据表
MT54V512H36AF-6	CYPRESS	获取价格	QDR SRAM, 512KX36, 2.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
MT54V512H36EF-10	CYPRESS	获取价格	QDR SRAM, 512KX36, 3ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
MT54V512H36EF-5	ROCHESTER	获取价格	512KX36 QDR SRAM, 2.2ns, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
MT54V512H36EF-5	CYPRESS	获取价格	QDR SRAM, 512KX36, 2.2ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
MT54V512H36EF-6	ROCHESTER	获取价格	512KX36 QDR SRAM, 2.5ns, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
MT54V512H36EF-7.5	CYPRESS	获取价格	QDR SRAM, 512KX36, 3ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
MT54W1MH18BF-4	CYPRESS	获取价格	QDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
MT54W1MH18BF-5	ROCHESTER	获取价格	1MX18 QDR SRAM, 0.45ns, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
MT54W1MH18BF-5	CYPRESS	获取价格	QDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
MT54W1MH18BF-6	CYPRESS	获取价格	QDR SRAM, 1MX18, 0.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165

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