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MT16VDDF6464HG-262 PDF预览

MT16VDDF6464HG-262

更新时间: 2024-11-06 03:01:43
品牌 Logo 应用领域
镁光 - MICRON 动态存储器双倍数据速率
页数 文件大小 规格书
31页 552K
描述
SMALL-OUTLINE DDR SDRAM DIMM

MT16VDDF6464HG-262 数据手册

 浏览型号MT16VDDF6464HG-262的Datasheet PDF文件第2页浏览型号MT16VDDF6464HG-262的Datasheet PDF文件第3页浏览型号MT16VDDF6464HG-262的Datasheet PDF文件第4页浏览型号MT16VDDF6464HG-262的Datasheet PDF文件第5页浏览型号MT16VDDF6464HG-262的Datasheet PDF文件第6页浏览型号MT16VDDF6464HG-262的Datasheet PDF文件第7页 
512MB, 1GB (x64)  
200-PIN DDR SODIMM  
MT16VDDF6464H – 512MB  
MT16VDDF12864H – 1GB  
SMALL-OUTLINE  
DDR SDRAM DIMM  
For the latest data sheet, please refer to the Micron Web  
site: www.micron.com/moduleds  
Features  
Figure 1: 200-Pin SODIMM (MO-224)  
200-pin, small-outline, dual in-line memory  
module (SODIMM)  
512MB Module  
Fast data transfer rates: PC1600, PC2100, and PC2700  
Utilizes 200 MT/s, 266 MT/s, or 333 MT/s DDR  
SDRAM components  
512MB (64 Meg x 64), 1GB (128 Meg x 64)  
VDD = VDDQ = +2.5V  
VDDSPD = +2.3V to +3.6V  
2.5V I/O (SSTL_2 compatible)  
Commands entered on each positive CK edge  
DQS edge-aligned with data for READs; center-  
aligned with data for WRITEs  
1GB Module  
Internal, pipelined double data rate (DDR)  
architecture; two data accesses per clock cycle  
Bidirectional data strobe (DQS) transmitted/  
received with data—i.e., source-synchronous data  
capture  
Differential clock inputs CK and CK#  
Four internal device banks for concurrent operation  
Programmable burst lengths: 2, 4, or 8  
Auto precharge option  
Auto Refresh and Self Refresh Modes  
7.8125µs maximum average periodic refresh interval  
Serial Presence Detect (SPD) with EEPROM  
Programmable READ CAS latency  
Gold edge contacts  
OPTIONS  
MARKING  
Package  
G
Y
200-pin SODIMM (standard)  
200-pin SODIMM (lead-free)1  
Frequency/CAS Latency2  
167 MHz (333 MT/s) CL = 2.5  
133 MHz (266 MT/s) CL = 2  
133 MHz (266 MT/s) CL = 2  
133 MHz (266 MT/s) CL = 2.5  
100 MHz (200 MT/s) CL = 2  
-335  
-262  
-26A  
-265  
-202  
NOTE: 1. Contact factory for availability of lead-free prod-  
ucts.  
2. CL = CAS (READ) latency.  
Table 1:  
Address Table  
512MB  
1GB  
8K  
8K  
Refresh Count  
8K (A0–A12)  
4 (BA0, BA1)  
32 Meg x 8  
1K (A0–A9)  
2 (S0#, S1#)  
8K (A0–A12)  
4 (BA0, BA1)  
64 Meg x 8  
Device Row Addressing  
Device Bank Addressing  
Device Configuration  
2K (A0–A9, A11)  
2 (S0#, S1#)  
Device Column Addressing  
Module Rank Addressing  
09005aef80a646bc  
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN  
1
©2003 Micron Technology, Inc.  
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.  

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