Datasheet > MSM548332

MSM548332

更新时间： 2022-12-13 04:56:09

品牌	Logo	应用领域
冲电气 - OKI		存储
页数	文件大小	规格书
23页	244K
描述
278,400-Word x 12-Bit Field Memory

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MSM548332 数据手册

¡ Semiconductor

MSM548332

2. Read address pointer increment operation

The read address pointer is incremented synchronized with RCLK when OE level is high.

Relationship between the RE and OE input levels,

Read Address pointer, and data output status

RCLK Rise

RE OE

Internal Read

Address Pointer

Data Output

Outputted

Hi-Z

Incremented

Stopped

Outputted

Hi-Z

When each read address pointer reaches the last address of a line, it stops at the last address

and no address increment occurs.

Initial Address Setting (Write/Read Independent)

Any read operations are prohibited in the read initial address set period. Similarly, any write

operationsareprohibitedinthewriteinitialaddresssetperiod.Notethatreadinitialaddresssetand

writeinitialaddresssetcanoccurindependently.Similarly,readaccesscanbeachievedindependently

from write initial address set period and write access can be achieved independently from read initial

address set cycles.

1. Write address setting

WADE/RX enables initial read address inputs. When WADE/RX is high, 9 bits of serial X

address (or line address) are input from WXAD.

Theoperationsaboveenableselectionofspecificlinesrandomlyandenablesthestartofserial

write access synchronized with write clock WCLK. Address for each line must be input

betweeneachlineaccess.Inotherwords,MSM548332'swriteisachievedina"linebyline"

manner. Any write operations are prohibited in the initial write address set periods.

Serialwriteinputenabletimet

mustbekeptforstartingaserialwritejustaftertheinitial

SWE

write address set period.

2. Read address setting

RADE/RX enables initial read address inputs.

When RADE/RX is high, 9 bits of serial X address (or line address) are input from RXAD.

Theoperationsaboveenableselectionofspecificlinesrandomlyandenablesthestartofserial

read access synchronized with read clocks, RCLK. Address for each line must be input

betweeneachlineaccess. Inotherwords, MSM548332'sreadoperationisachievedin"lineby

line" manner.

Any read operations are prohibited in the initial read address set periods. Serial read

operations are prohibited while RADE/RX is high. Serial read port enable time t

kept for starting a serial read just after the initial read address set period.

must be

SRE

Initial Address Reset Modes (Write/Read Independent)

Theinitialaddressresetmodesreplacecomplicatedreadorwriteinitialaddresssettingswithsimple

resetcycles.InitialaddressresetmodesareselectedbyRRhighduringreadandWR/TRhighduring

write. Asinnormalreadorwriteaddresssettings, anyreadoperationsareprohibitedintheread

addressresetcycles.Similarly,anywriteoperationsareprohibitedintheinitialwriteaddressreset

cycles.Notethatreadinitialaddressresetandwriteinitialaddressresetcanoccurindependently.

Similarly, read access can be achieved independently from write initial address reset cycles and write

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与MSM548332相关器件

型号	品牌	描述	获取价格	数据表
MSM548333	OKI	240,384-Word x 8-bit + 240,384-Word x 4-bit Triple Port type Field Memory	获取价格
MSM548512D-10GS	OKI	Pseudo Static RAM, 512KX8, 100ns, CMOS, PDSO32, 0.525 INCH, PLASTIC, SSOP-32	获取价格
MSM548512D-10RS	OKI	Pseudo Static RAM, 512KX8, 100ns, CMOS, PDIP32, 0.600 INCH, PLASTIC, DIP-32	获取价格
MSM548512D-12GS	OKI	Pseudo Static RAM, 512KX8, 120ns, CMOS, PDSO32, 0.525 INCH, PLASTIC, SSOP-32	获取价格
MSM548512D-12RS	OKI	Pseudo Static RAM, 512KX8, 120ns, CMOS, PDIP32, 0.600 INCH, PLASTIC, DIP-32	获取价格
MSM548512D-80RS	OKI	Pseudo Static RAM, 512KX8, 80ns, CMOS, PDIP32, 0.600 INCH, PLASTIC, DIP-32	获取价格

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