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MSM548262-80TS-K PDF预览

MSM548262-80TS-K

更新时间: 2024-02-16 20:33:25
品牌 Logo 应用领域
冲电气 - OKI 动态存储器
页数 文件大小 规格书
37页 459K
描述
262,144-Word x 8-Bit Multiport DRAM

MSM548262-80TS-K 技术参数

生命周期:Transferred零件包装代码:TSOP2
包装说明:TSOP2,针数:44
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.02风险等级:5.58
访问模式:FAST PAGE最长访问时间:80 ns
其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH; 512 X 8 SAM PORTJESD-30 代码:R-PDSO-G40
长度:18.41 mm内存密度:2097152 bit
内存集成电路类型:VIDEO DRAM内存宽度:8
功能数量:1端口数量:2
端子数量:40字数:262144 words
字数代码:256000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX8封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
宽度:10.16 mmBase Number Matches:1

MSM548262-80TS-K 数据手册

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¡ Semiconductor  
MSM548262  
Notes: 1. Exposure beyond the "Absolute Maximum Ratings" may cause permanent damage  
to the device.  
2. All voltages are referenced to V .  
SS  
3. These parameters depend on the cycle rate.  
4. These parameters depend on output loading. Specified values are obtained with the  
output open.  
5. An initial pause of 200 ms is required after power up followed by any 8 RAS cycles  
(TRG = "high") and any 8 SC cycles before proper device operation is achieved.  
In the case of using an internal refresh counter, a minimum of 8 CAS before RAS  
cycles instead of 8 RAS cycles are required.  
6. AC measurements assume t = 5 ns.  
T
7. V (Min.)andV (Max.)arereferencelevelsformeasuringtimingofinputsignals.  
IH  
IL  
Also, transition times are measured between V and V .  
IH  
IL  
8. RAM port outputs are measured with a load equivalent to 1 TTL load and 50 pF.  
DOUT reference levels : V /V = 2.0 V/0.8 V.  
OH  
OL  
9. SAM port outputs are measured with a load equivalent to 1 TTL load and 30 pF.  
DOUT reference levels : V /V = 2.0 V/0.8 V.  
OH  
OL  
10. t  
(Max.), t  
(Max.), t  
(Max.) and t  
(Max.) define the time at which the  
OFF  
OEZ  
SDZ  
SEZ  
outputsachievetheopencircuitcondition, andarenotreferencedtooutputvoltage  
levels. This parameter is sampled and not 100% tested.  
11. Either t  
or t  
must be satisfied for a read cycle.  
RCH  
RRH  
12. These parameters are referenced to CAS leading edge of early write cycles, and to  
WE leading edge in TRG controlled write cycles and read modify write cycles.  
13. t  
, t  
, t  
and t  
are not restrictive operating parameters.  
AWD  
WCS RWD CWD  
They are included in the data sheet as electrical characteristics only.  
If t t (Min.), the cycle is an early write cycle, and the data out pin will  
WCS  
WCS  
remain open circuit throughout the entire cycle; If t  
t  
(Min.), t  
t  
RWD RWD  
CWD CWD  
(Min.) and t  
t  
(Min.), the cycle is a read modify write cycle, and the data  
AWD AWD  
out will contain data read from the selected cell; If neither of the above sets of  
conditions are satisfied, the condition of the data out is indeterminate.  
14. Operation within the t  
(Max.) limit ensures that t  
(Max.) can be met.  
RCD  
RAC  
t
(Max.)isspecifiedasareferencepointonly:Ift  
(Max.) limit, then access time is controlled by t  
isgreaterthanthespecified  
RCD  
RCD  
t
.
RCD  
CAC  
15. Operation within the t  
(Max.) limit ensures that t  
(Max.) can be met. t  
RAD  
RAC  
RAD  
RAD  
(Max.)isspecifiedasareferencepointonly:Ift  
isgreaterthanthespecifiedt  
RAD  
(Max.) limit, then access time is controlled by t  
16. Input levels at the AC testing are 3.0 V/0 V.  
.
AA  
17. Address (A0 - A8) may be changed two times or less while RAS = V .  
IL  
18. Address (A0 - A8) may be changed once or less while CAS = V and RAS = V .  
IH  
IL  
19. This is guaranteed by design. (t  
/t  
= t  
/t  
- output transition time)  
SOH COH  
SCA CAC  
This parameter is not 100% tested.  
9/37  

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