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MSM51V4221C-30JA PDF预览

MSM51V4221C-30JA

更新时间: 2024-01-01 11:36:07
品牌 Logo 应用领域
冲电气 - OKI 存储内存集成电路光电二极管
页数 文件大小 规格书
16页 233K
描述
262,263-Word × 4-Bit Field Memory

MSM51V4221C-30JA 技术参数

生命周期:Transferred零件包装代码:ZIP
包装说明:ZIP,针数:20
Reach Compliance Code:unknownHTS代码:8542.32.00.71
风险等级:5.26Is Samacsys:N
JESD-30 代码:R-PZIP-T20长度:25.5 mm
内存密度:1048576 bit内存集成电路类型:MEMORY CIRCUIT
内存宽度:4功能数量:1
端子数量:20字数:262144 words
字数代码:256000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX4封装主体材料:PLASTIC/EPOXY
封装代码:ZIP封装形状:RECTANGULAR
封装形式:IN-LINE认证状态:Not Qualified
座面最大高度:10.16 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:THROUGH-HOLE
端子节距:1.27 mm端子位置:ZIG-ZAG
宽度:2.8 mmBase Number Matches:1

MSM51V4221C-30JA 数据手册

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FEDS51V4221C-03  
This version: Oct. 2000  
Previous version: Feb. 2000  
1
Semiconductor  
MSM51V4221C  
262,263-Word × 4-Bit Field Memory  
GENERAL DESCRIPTION  
The OKI MSM51V4221C is a high performance 1-Mbit, 256K × 4-bit, Field Memory. It is designed for high-  
speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital movies and Multi-media  
systems. It is a FRAM for wide or low end use as general commodity TVs and VTRs, exclusively. The  
MSM51V4221C is not designed for the other use or high end use in medical systems, professional graphics  
systems which require long term picture, and data storage systems and others. The 1-Mbit capacity fits one field of  
a conventional NTSC TV screen.  
Each of the 4-bit planes has separate serial write and read ports. These employ independent control clocks to  
support asynchronous read and write operations. Different clock rates are also supported that allow alternate data  
rates between write and read data streams.  
The MSM51V4221C provides high speed FIFO, First-In First-Out, operation without external refreshing: it  
refreshes its DRAM storage cells automatically, so that it appears fully static to the users.  
Moreover, fully static type memory cells and decoders for serial access enable refresh free serial access operation,  
so that the serial read and/or write control clock can be halted high or low for any duration as long as the power is  
on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic.  
The MSM51V4221B’s function is simple, and similar to a digital delay device whose delay-bit-length is easily set  
by reset timing. The delay length, number of read delay clocks between write and read, is determined by externally  
controlled write and read reset timings.  
Additional SRAM serial registers, or line buffers for the initial access of 256 × 4-bit enable high speed first-bit-  
access with no clock delay just after the write or read reset timings.  
The MSM51V4221C is similar in operation and functionality to OKI 2-Mbit Field Memory MSM51V8221A.  
1/16  

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