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MSM51V4222C-30RA PDF预览

MSM51V4222C-30RA

更新时间: 2024-11-26 10:45:23
品牌 Logo 应用领域
冲电气 - OKI 存储
页数 文件大小 规格书
16页 234K
描述
262,263-Word × 4-Bit Field Memory

MSM51V4222C-30RA 数据手册

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FEDS51V4222C-03  
This version: Oct. 2000  
Previous version: Feb. 2000  
1
Semiconductor  
MSM51V4222C  
262,263-Word × 4-Bit Field Memory  
GENERAL DESCRIPTION  
The OKI MSM51V4222C is a high performance 1-Mbit, 256 K × 4-bit, Field Memory. It is designed for high-  
speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital movies and Multi-media  
systems. It is a FRAM for wide or low end use as general commodity TVs and VTRs, exclusively. The  
MSM51V4222C is not designed for the other use or high end use in medical systems, professional graphics  
systems which require long term picture, and data storage systems and others. The 1-Mbit capacity fits one field of  
a conventional NTSC TV screen and cascaded directly without any delay devices among the MSM51V4222C.  
(Cascading of MSM51V4222C provides larger storage depth or a longer delay).  
Each of the 4-bit planes has separate serial write and read ports. These employ independent control clocks to  
support asynchronous read and write operations. Different clock rates are also supported that allow alternate data  
rates between write and read data streams.  
The MSM51V4222C provides high speed FIFO, First-In First-Out, operation without external refreshing: it  
refreshes its DRAM storage cells automatically, so that it appears fully static to the users.  
Moreover, fully static type memory cells and decoders for serial access enable refresh free serial access operation,  
so that the serial read and/or write control clock can be halted high or low for any duration as long as the power is  
on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic.  
The MSM51V4222C’s function is simple, and similar to a digital delay device whose delay-bit-length is easily set  
by reset timing. The delay length, number of read delay clocks between write and read, is determined by externally  
controlled write and read reset timings.  
Additional SRAM serial registers, or line buffers for the initial access of 256 × 4-bit enable high speed first-bit-  
access with no clock delay just after the write or read reset timings.  
The MSM51V4222C is similar in operation and functionality to OKI 2-Mbit Field Memory MSM51V8222A.  
1/16  

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