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MM74HCT643J PDF预览

MM74HCT643J

更新时间： 2024-11-22 23:02:43
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
4页 134K
描述
Inverting Octal TRI-STATE Transceiver

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中文翻译

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MM74HCT643J 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP20,.3Reach Compliance Code：unknown
风险等级：5.5其他特性：INVERTED OUTPUTS PORT A TO B
控制类型：COMMON CONTROL计数方向：BIDIRECTIONAL
系列：HCTJESD-30 代码：R-GDIP-T20
JESD-609代码：e0长度：24.51 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS TRANSCEIVER
最大I（ol）：0.006 A位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP20,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
Prop。Delay @ Nom-Sup：29 ns传播延迟（tpd）：38 ns
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：7.62 mm
Base Number Matches：1

MM74HCT643J 数据手册

 浏览型号MM74HCT643J的Datasheet PDF文件第2页浏览型号MM74HCT643J的Datasheet PDF文件第3页浏览型号MM74HCT643J的Datasheet PDF文件第4页 
February 1988  
MM54HCT640/MM74HCT640  
Inverting Octal TRI-STATE Transceiver  
É
MM54HCT643/MM74HCT643  
True-Inverting Octal TRI-STATE Transceiver  
General Description  
TheseTRI-STATEbi-directionaltransceiversutilizeadvanced  
silicon-gate CMOS technology and are intended for two-way  
asynchronous communication between data buses. They  
have high drive current outputs which enable high speed  
operation even when driving large bus capacitances. These  
circuits possess the low power consumption of CMOS cir-  
cuitry, yet have speeds comparable to low power Schottky  
TTL circuits.  
MM74HCT640 transfers inverted data from one bus to the  
other. The MM54HCT643/MM74HCT643 transfers inverted  
data from the A bus to the B bus and non-inverted data from  
the B bus to the A bus.  
MM54HCT/MM74HCT devices are intended to interface be-  
tween TTL and NMOS components and standard CMOS  
devices. These parts are also plug-in replacements for LS-  
TTL devices and can be used to reduce power consumption  
in existing designs.  
All devices are TTL input compatible and can drive up to 15  
LS-TTL loads, and all inputs are protected from damage due  
Features  
Y
to static discharge by diodes to V  
and ground.  
CC  
TTL input compatible  
Both the MM54HCT640/MM74HCT640 and the  
MM54HCT643/ MM74HCT643 have one active low enable  
input (G), and a direction control (DIR). When the DIR input  
is high, data flows from the A inputs to the B outputs. When  
DIR is low, data flows from B to A. The MM54HCT640/  
Y
Octal TRI-STATE outputs for mP bus applications:  
6 mA, typical  
Y
High speed: 16 ns typical propagation delay  
Y
Low power: 80 mA maximum (74HCT)  
Connection Diagram  
Dual-In-Line Packages  
TL/F/5370–1  
TL/F/5370–2  
Top View  
Order Number MM54HCT643 or MM74HCT643  
Top View  
Order Number MM54HCT640 or MM74HCT640  
Truth Table  
Control  
Inputs  
Operation  
G
L
DIR  
L
640  
643  
B data to A bus B data to A bus  
A data to B bus A data to B bus  
L
H
H
X
Isolation  
Isolation  
e
e e  
high level, L low level, X irrelevant  
H
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.  
C
1995 National Semiconductor Corporation  
TL/F/5370  
RRD-B30M105/Printed in U. S. A.  
1234

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