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MM74HCT151M PDF预览

MM74HCT151M

更新时间: 2024-11-24 13:11:39
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美国国家半导体 - NSC 复用器
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4页 138K
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MM74HCT151M 数据手册

 浏览型号MM74HCT151M的Datasheet PDF文件第2页浏览型号MM74HCT151M的Datasheet PDF文件第3页浏览型号MM74HCT151M的Datasheet PDF文件第4页 
November 1995  
MM54HCT151/MM74HCT151  
8-Channel Digital Multiplexer  
General Description  
This high speed Digital multiplexer utilizes advanced silicon-  
gate CMOS technology. Along with the high noise immunity  
and low power dissipation of standard CMOS integrated cir-  
cuits, it possesses the ability to drive 10 LS-TTL loads. The  
MM54HCT151/MM74HCT151 selects one of the 8 data  
sources, depending on the address presented on the A, B,  
and C inputs. It features both true (Y) and complement (W)  
outputs. The STROBE input must be at a low logic level to  
enable this multiplexer. A high logic level at the STROBE  
forces the W output high and the Y output low.  
devices. These parts are also plug-in replacements for LS-  
TTL devices and can be used to reduce power consumption  
in existing designs.  
Features  
Y
Typical propagation delay: 20 ns  
Y
Low quiescent supply current: 40 mA maximum  
(74HCT Series)  
Y
Low input current: 1 mA maximum  
Y
Fanout of 10 LS-TTL loads  
MM54HCT/MM74HCT devices are intended to interface be-  
tween TTL and NMOS components and standard CMOS  
Y
TTL input compatible  
Connection and Logic Diagrams  
Truth Table  
Dual-In-Line Package  
Inputs  
Select  
Outputs  
Strobe  
S
Y
W
C
B
A
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
L
L
L
L
L
L
L
L
L
H
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
H
e
e
e
Low Level, X Don’t Care  
H
High Level, L  
TL/F/9399–1  
e
D0, D1...D7  
the level of the respective D input  
Top View  
Order Number MM54HCT151 or MM74HCT151  
TL/F/9399–2  
C
1995 National Semiconductor Corporation  
TL/F/9399  
RRD-B30M115/Printed in U. S. A.  

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