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MM74HCT151N PDF预览

MM74HCT151N

更新时间: 2024-11-23 23:02:43
品牌 Logo 应用领域
美国国家半导体 - NSC 解复用器逻辑集成电路光电二极管
页数 文件大小 规格书
4页 138K
描述
8-Channel Digital Multiplexer

MM74HCT151N 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:PLASTIC, DIP-16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.35
Is Samacsys:N系列:HCT
JESD-30 代码:R-PDIP-T16JESD-609代码:e0
长度:19.305 mm负载电容(CL):50 pF
逻辑集成电路类型:MULTIPLEXER最大I(ol):0.0048 A
功能数量:1输入次数:8
输出次数:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
Prop。Delay @ Nom-Sup:58 ns传播延迟(tpd):58 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Multiplexer/Demultiplexers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

MM74HCT151N 数据手册

 浏览型号MM74HCT151N的Datasheet PDF文件第2页浏览型号MM74HCT151N的Datasheet PDF文件第3页浏览型号MM74HCT151N的Datasheet PDF文件第4页 
November 1995  
MM54HCT151/MM74HCT151  
8-Channel Digital Multiplexer  
General Description  
This high speed Digital multiplexer utilizes advanced silicon-  
gate CMOS technology. Along with the high noise immunity  
and low power dissipation of standard CMOS integrated cir-  
cuits, it possesses the ability to drive 10 LS-TTL loads. The  
MM54HCT151/MM74HCT151 selects one of the 8 data  
sources, depending on the address presented on the A, B,  
and C inputs. It features both true (Y) and complement (W)  
outputs. The STROBE input must be at a low logic level to  
enable this multiplexer. A high logic level at the STROBE  
forces the W output high and the Y output low.  
devices. These parts are also plug-in replacements for LS-  
TTL devices and can be used to reduce power consumption  
in existing designs.  
Features  
Y
Typical propagation delay: 20 ns  
Y
Low quiescent supply current: 40 mA maximum  
(74HCT Series)  
Y
Low input current: 1 mA maximum  
Y
Fanout of 10 LS-TTL loads  
MM54HCT/MM74HCT devices are intended to interface be-  
tween TTL and NMOS components and standard CMOS  
Y
TTL input compatible  
Connection and Logic Diagrams  
Truth Table  
Dual-In-Line Package  
Inputs  
Select  
Outputs  
Strobe  
S
Y
W
C
B
A
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
L
L
L
L
L
L
L
L
L
H
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
H
e
e
e
Low Level, X Don’t Care  
H
High Level, L  
TL/F/9399–1  
e
D0, D1...D7  
the level of the respective D input  
Top View  
Order Number MM54HCT151 or MM74HCT151  
TL/F/9399–2  
C
1995 National Semiconductor Corporation  
TL/F/9399  
RRD-B30M115/Printed in U. S. A.  

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