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MM74HC4017 PDF预览

MM74HC4017

更新时间: 2024-10-27 23:02:43
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美国国家半导体 - NSC 计数器
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6页 127K
描述
Decade Counter/Divider with 10 Decoded Outputs

MM74HC4017 数据手册

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January 1988  
MM54HC4017/MM74HC4017  
Decade Counter/Divider with 10 Decoded Outputs  
General Description  
The MM54HC4017/MM74HC4017 is a 5-stage Johnson  
counter with 10 decoded outputs that utilizes advanced sili-  
con-gate CMOS technology. Each of the decoded outputs is  
normally low and sequentially goes high on the low to high  
transition of the clock input. Each output stays high for one  
clock period of the 10 clock period cycle. The CARRY out-  
put transitions low to high after OUTPUT 9 goes low, and  
can be used in conjunction with the CLOCK ENABLE to  
cascade several stages. The CLOCK ENABLE input dis-  
ables counting when in the high state. A RESET input is  
also provided which when taken high sets all the decoded  
outputs low except output 0.  
up to 10 low power Schottky equivalent loads. All inputs are  
protected from damage due to static discharge by diodes  
from V  
CC  
and ground.  
Features  
Y
Wide power supply range: 26V  
Y
Typical operating frequency: 30 MHz  
Y
Fanout of 10 LS-TTL loads  
Y
Low quiescent current: 80 mA (74HC Series)  
Y
Low input current: 1.0 mA  
The MM54HC4017/MM74HC4017 is functionally and pinout  
equivalent to the CD4017BM/CD4017BC. It can drive  
Connection Diagram  
Dual-In-Line and Flat Package  
TL/F/5351–1  
Order Number MM54HC4017 or MM74HC4017  
C
1995 National Semiconductor Corporation  
TL/F/5351  
RRD-B30M105/Printed in U. S. A.  

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