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MM74HC32_08 PDF预览

MM74HC32_08

更新时间: 2024-11-02 12:05:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
9页 329K
描述
Quad 2-Input OR Gate

MM74HC32_08 数据手册

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February 2008  
MM74HC32  
Quad 2-Input OR Gate  
Features  
General Description  
Typical propagation delay: 10ns  
The MM74HC32 OR gates utilize advanced silicon-gate  
CMOS technology to achieve operating speeds similar to  
LS-TTL gates with the low power consumption of stan-  
dard CMOS integrated circuits. All gates have buffered  
outputs providing high noise immunity and the ability to  
drive 10 LS-TTL loads. The 74HC logic family is func-  
tionally as well as pin-out compatible with the standard  
74LS logic family. All inputs are protected from damage  
Wide power supply range: 2V–6V  
Low quiescent current: 20µA maximum (74HC Series)  
Low input current: 1µA maximum  
Fanout of 10 LS-TTL loads  
due to static discharge by internal diode clamps to V  
and ground.  
CC  
Ordering Information  
Package  
Order Number Number  
Package Description  
MM74HC32M  
MM74HC32SJ  
MM74HC32MTC  
MM74HC32N  
M14A  
M14D  
MTC14  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.  
All packages are lead free per JEDEC: J-STD-020B standard.  
Connection Diagram  
Logic Diagram  
Pin Assignments for DIP, SOIC, SOP and TSSOP  
Y = A + B  
(1 of 4)  
Top View  
©1983 Fairchild Semiconductor Corporation  
MM74HC32 Rev. 1.3.0  
www.fairchildsemi.com  

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