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MM74HC299N/A+ PDF预览

MM74HC299N/A+

更新时间: 2024-11-02 13:11:39
品牌 Logo 应用领域
美国国家半导体 - NSC 移位寄存器
页数 文件大小 规格书
7页 185K
描述
IC,SHIFT REGISTER,HC-CMOS,DIP,20PIN,PLASTIC

MM74HC299N/A+ 技术参数

是否Rohs认证:不符合生命周期:Transferred
包装说明:DIP, DIP20,.3Reach Compliance Code:unknown
风险等级:5.85Is Samacsys:N
JESD-30 代码:R-PDIP-T20JESD-609代码:e0
位数:8功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:2/6 V子类别:Shift Registers
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

MM74HC299N/A+ 数据手册

 浏览型号MM74HC299N/A+的Datasheet PDF文件第2页浏览型号MM74HC299N/A+的Datasheet PDF文件第3页浏览型号MM74HC299N/A+的Datasheet PDF文件第4页浏览型号MM74HC299N/A+的Datasheet PDF文件第5页浏览型号MM74HC299N/A+的Datasheet PDF文件第6页浏览型号MM74HC299N/A+的Datasheet PDF文件第7页 
January 1988  
MM54HC299/MM74HC299  
8-Bit TRI-STATE Universal Shift Register  
General Description  
É
This 8-bit TRI-STATE shift/storage register utilizes advanced  
silicon-gate CMOS technology. Along with the low power  
consumption and high noise immunity of standard CMOS  
integrated circuits, it has the ability to drive 15 LS-TTL  
loads. This circuit also features operating speeds compara-  
ble to the equivalent low power Schottky device.  
permits data applied to the input/output lines to be clocked  
into the register. Reading out of the register can be done  
while the outputs are enabled in any mode. A direct overrid-  
ing CLEAR input is provided to clear the register whether  
the outputs are enabled or disabled.  
The 54HC/74HC logic family is functionally as well as pinout  
compatible with the standard 54LS/74LS logic family. All  
inputs are protected from damage due to static discharge by  
The MM54HC299/MM74HC299 features multiplexed in-  
puts/outputs to achieve full 8-bit data handling in a single  
20-pin package. Due to the large output drive capability and  
TRI-STATE feature, this device is ideally suited for interfac-  
ing with bus lines in a bus oriented system.  
internal diode clamps to V  
and ground.  
CC  
Features  
Y
Two function select inputs and two output control inputs are  
used to choose the mode of operation as listed in the func-  
tion table. Synchronous parallel loading is accomplished by  
taking both function select lines S0 and S1 high. This places  
the TRI-STATE outputs in a high impedance state, which  
Typical operating frequency 40 MHz  
Y
Y
Y
Y
Typical propagation delay: 20 ns  
Low quiescent current: 80 mA maximum (74HC)  
High output drive for bus applications  
Low quiescent current: 1 mA maximum  
Connection Diagram  
Dual-In-Line Package  
TL/F/5207–1  
Order Number MM54HC299 or MM74HC299  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/5207  
RRD-B30M105/Printed in U. S. A.  

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