MM74HC280N/A+

更新时间： 2024-11-25 13:01:59

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MM74HC280N/A+ 数据手册

January 1988

MM54HC280/MM74HC280

9-Bit Odd/Even Parity Generator/Checker

General Description

Features

The MM54HC280/MM74HC280 utilizes advanced silicon-

gate CMOS technology to achieve the high noise immunity

and low power consumption of standard CMOS integrated

circuits. It possesses the ability to drive 10 LS-TTL loads.

Typical propagation delay: 28 ns

Wide power supply range: 2V–6V

Low quiescent current: 80 mA maximum (74HC)

Low input current: 1 mA maximum

Fanout of 10 LS-TTL loads

This parity generator/checker features odd/even outputs to

facilitate operation of either odd or even parity applications.

The word length capability is easily expanded by cascading

devices. The 54HC/74HC logic family is speed, function,

and pinout compatible with the standard 54LS/74LS family.

All inputs are protected from damage due to static dis-

charge by internal diode clamps to V

and ground.

Connection Diagram

Dual-In-Line Package

TL/F/5121–1

Order Number MM54HC280 or MM74HC280

Function Table

Numbers of Inputs A

Outputs

thru 1 that are High

R Even

R Odd

0, 2, 4, 6, 8

1, 3, 5, 7, 9

low level

high level,

1995 National Semiconductor Corporation

TL/F/5121

RRD-B30M105/Printed in U. S. A.

12 3 4

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