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MM74HC283J PDF预览

MM74HC283J

更新时间: 2024-11-02 05:08:31
品牌 Logo 应用领域
美国国家半导体 - NSC 运算电路逻辑集成电路
页数 文件大小 规格书
6页 121K
描述
4-Bit Binary Adder with Fast Carry

MM74HC283J 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:J16A, 16 PINReach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.28
Is Samacsys:N其他特性:FULL ADDER; WITH INTERNAL CARRY LOOKAHEAD; PERMITS RIPPLE CARRY CASCADING
系列:HC/UHJESD-30 代码:R-GDIP-T16
JESD-609代码:e0长度:19.43 mm
负载电容(CL):50 pF逻辑集成电路类型:ADDER/SUBTRACTOR
位数:4功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
传播延迟(tpd):41 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Arithmetic Circuits
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

MM74HC283J 数据手册

 浏览型号MM74HC283J的Datasheet PDF文件第2页浏览型号MM74HC283J的Datasheet PDF文件第3页浏览型号MM74HC283J的Datasheet PDF文件第4页浏览型号MM74HC283J的Datasheet PDF文件第5页浏览型号MM74HC283J的Datasheet PDF文件第6页 
January 1988  
MM54HC283/MM74HC283  
4-Bit Binary Adder with Fast Carry  
General Description  
Features  
Y
Full-carry look-ahead across the four bits  
This full adder performs the addition of two 4-bit binary num-  
bers utilizing advanced silicon-gate CMOS technology. The  
sum (R) outputs are provided for each bit and the resultant  
carry (C4) is obtained from the fourth bit. These adders fea-  
ture full internal look ahead across all four bits. This pro-  
vides the system designer with partial look-ahead perform-  
ance at the economy and reduced package count of a rip-  
ple-carry implementation.  
Y
Systems achieve partial look-ahead performance  
with the economy of ripple carry  
Y
Y
Y
Wide supply range: 2V to 6V  
Low quiescent power consumption: 8 mA at 25 C  
§
Low input current: 1 mA maximum  
The adder logic, including the carry, is implemented in its  
true form meaning that the end-around carry can be accom-  
plished without the need for logic or level inversion. All in-  
puts are protected from damage due to static discharge by  
internal diode clamps to V  
and ground.  
CC  
Connection Diagram  
Dual-In-Line Package  
TL/F/5332–1  
Top View  
Order Number MM54HC283 or MM74HC283  
C
1995 National Semiconductor Corporation  
TL/F/5332  
RRD-B30M105/Printed in U. S. A.  

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