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MM74HC253J PDF预览

MM74HC253J

更新时间: 2024-11-24 23:02:43
品牌 Logo 应用领域
美国国家半导体 - NSC 解复用器逻辑集成电路
页数 文件大小 规格书
4页 115K
描述
Dual 4-Channel TRI-STATE Multiplexer

MM74HC253J 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:DIP-16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.82
Is Samacsys:N其他特性:ENABLE TIME @ RL=1K OHM
系列:HC/UHJESD-30 代码:R-GDIP-T16
JESD-609代码:e0长度:19.43 mm
负载电容(CL):50 pF逻辑集成电路类型:MULTIPLEXER
最大I(ol):0.004 A功能数量:2
输入次数:4输出次数:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
Prop。Delay @ Nom-Sup:35 ns传播延迟(tpd):158 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Multiplexer/Demultiplexers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

MM74HC253J 数据手册

 浏览型号MM74HC253J的Datasheet PDF文件第2页浏览型号MM74HC253J的Datasheet PDF文件第3页浏览型号MM74HC253J的Datasheet PDF文件第4页 
January 1988  
MM54HC253/MM74HC253  
Dual 4-Channel TRI-STATE Multiplexer  
É
General Description  
The MM54HC253/MM74HC253 utilizes advanced silicon-  
gate CMOS technology to achieve the low power consump-  
tion and high noise immunity of standard CMOS integrated  
circuits, along with the capability to drive 10 LS-TTL loads.  
The large output drive and TRI-STATE features of this de-  
vice make it ideally suited for interfacing with bus lines in  
bus organized systems. When the output control input is  
taken high, the multiplexer outputs are sent into a high im-  
pedance state.  
The 54HC/74HC logic family is functionally and pinout com-  
patible with the standard 54LS/74LS logic family. All inputs  
are protected from damage due to static discharge by inter-  
nal diode clamps to V  
and ground.  
CC  
Features  
Y
Typical propagation delay: 24 ns  
Y
Y
Y
Y
Wide power supply range: 2V6V  
Low quiescent current: 80 mA maximum (74HC Series)  
Low input current: 1 mA maximum  
Fanout of 10 LS-TTL loads  
When the output control is held low, the associated multi-  
plexer chooses the correct output channel for the given in-  
put signals determined by the select A and B inputs.  
Connection Diagram  
Dual-In-Line Package  
TL/F/5108–1  
Order Number MM54HC253 or MM74HC253  
Truth Table  
Select  
Inputs  
Output  
Control  
Data Inputs  
Output  
Y
B
A
C0  
C1  
C2  
C3  
G
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
L
H
L
L
L
L
L
L
L
L
Z
L
H
L
H
L
H
L
H
X
X
X
X
X
X
H
H
Select inputs A and B are common to both sections.  
e
e
e
e
irrelevant, Z high impedance (off).  
H
high level, L  
low level, X  
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.  
C
1995 National Semiconductor Corporation  
TL/F/5108  
RRD-B30M105/Printed in U. S. A.  

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