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MM74HC259MTCX PDF预览

MM74HC259MTCX

更新时间： 2024-11-25 13:11:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
7页 79K
描述
D Latch, HC/UH Series, 1-Func, Low Level Triggered, 1-Bit, True Output, CMOS, PDSO16, 4.40 MM, MO-153, TSSOP-16

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MM74HC259MTCX 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP16,.25
针数：16Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.61
Samacsys Confidence：Samacsys Status：Released
Samacsys PartID：582302Samacsys Pin Count：16
Samacsys Part Category：Undefined or MiscellaneousSamacsys Package Category：Other
Samacsys Footprint Name：SOP65P640X90-16NSamacsys Released Date：2017-01-11 16:35:06
Is Samacsys：N其他特性：1:8 DMUX FOLLOWED BY LATCH
系列：HC/UHJESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：5 mm
负载电容（CL）：50 pF逻辑集成电路类型：D LATCH
最大I（ol）：0.004 A湿度敏感等级：1
位数：1功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260电源：2/6 V
Prop。Delay @ Nom-Sup：46 ns传播延迟（tpd）：250 ns
认证状态：Not Qualified座面最大高度：1.1 mm
子类别：FF/Latches最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：LOW LEVEL
宽度：4.4 mmBase Number Matches：1

MM74HC259MTCX 数据手册

 浏览型号MM74HC259MTCX的Datasheet PDF文件第2页浏览型号MM74HC259MTCX的Datasheet PDF文件第3页浏览型号MM74HC259MTCX的Datasheet PDF文件第4页浏览型号MM74HC259MTCX的Datasheet PDF文件第5页浏览型号MM74HC259MTCX的Datasheet PDF文件第6页浏览型号MM74HC259MTCX的Datasheet PDF文件第7页 
September 1983  
Revised February 1999  
MM74HC259  
8-Bit Addressable Latch/3-to-8 Line Decoder  
inputs. To eliminate the possibility of entering erroneous  
data into the latches, the enable should be held HIGH  
(inactive) while the address lines are changing.  
General Description  
The MM74HC259 device utilizes advanced silicon-gate  
CMOS technology to implement an 8-bit addressable latch,  
designed for general purpose storage applications in digital  
systems.  
If enable is held HIGH and CLEAR is taken LOW all eight  
latches are cleared to a LOW state. If enable is LOW all  
latches except the addressed latch will be cleared. The  
addressed latch will instead follow the D input, effectively  
implementing a 3-to-8 line decoder.  
The MM74HC259 has a single data input (D), 8 latch out-  
puts (Q1–Q8), 3 address inputs (A, B, and C), a common  
enable input (G), and a common CLEAR input. To operate  
this device as an addressable latch, data is held on the D  
input, and the address of the latch into which the data is to  
be entered is held on the A, B, and C inputs. When  
ENABLE is taken LOW the data flows through to the  
addressed output. The data is stored when ENABLE transi-  
tions from LOW-to-HIGH. All unaddressed latches will  
remain unaffected. With enable in the HIGH state the  
device is deselected, and all latches remain in their previ-  
ous state, unaffected by changes on the data or address  
All inputs are protected from damage due to static dis-  
charge by diodes to VCC and ground.  
Features  
■ Typical propagation delay: 18 ns  
■ Wide supply range: 2–6V  
■ Low input current: 1 µA maximum  
■ Low quiescent current: 80 µA maximum (74HC Series)  
Ordering Code:  
Order Number  
MM74HC259M  
MM74HC259SJ  
MM74HC259MTC  
MM74HC259N  
Package Number Package Description  
M16A  
M16D  
MTC16  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Latch Selection Table  
Pin Assignments for DIP, SOIC, SOP and TSSOP  
Select Inputs  
Latch  
C
L
B
L
A
L
Addressed  
0
1
2
3
4
5
6
7
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
H = HIGH level, L = LOW level  
D = the level at the data input  
Q
the level of Q (i = 0, 1...7, as appropriate)  
i
i0  
Top View  
before the indicated steady-state input  
conditions were established.  
© 1999 Fairchild Semiconductor Corporation  
DS005006.prf  
www.fairchildsemi.com  
1234567

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MM74HC259MTCX 替代型号

型号 品牌 替代类型 描述 数据表
SN74HC174DR TI

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SN74HC112DR TI

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 DUAL J-NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN74HC174D TI

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 HEX D-TYPE FLIP-FLOPS WITH CLEAR

与MM74HC259MTCX相关器件

型号 品牌 获取价格 描述 数据表
MM74HC259MX ROCHESTER

获取价格

 		D Latch, HC/UH Series, 1-Func, Low Level Triggered, 1-Bit, True Output, CMOS, PDSO16, 0.15
MM74HC259MX TI

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 		HC/UH SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO16, PLASTIC, SO-16
MM74HC259MX FAIRCHILD

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 		D Latch, HC/UH Series, 1-Func, Low Level Triggered, 1-Bit, True Output, CMOS, PDSO16, 0.15
MM74HC259MX_NL FAIRCHILD

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 		D Latch, HC/UH Series, 1-Func, Low Level Triggered, 1-Bit, True Output, CMOS, PDSO16, 0.15
MM74HC259N FAIRCHILD

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 		8-Bit Addressable Latch/3-to-8 Line Decoder
MM74HC259N/A+ NSC

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 		IC,LATCH,SINGLE,8-BIT,HC-CMOS,DIP,16PIN,PLASTIC
MM74HC259N/B+ NSC

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 		IC,LATCH,SINGLE,8-BIT,HC-CMOS,DIP,16PIN,PLASTIC
MM74HC259SJ FAIRCHILD

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 		8-Bit Addressable Latch/3-to-8 Line Decoder
MM74HC259SJ ROCHESTER

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 		D Latch, HC/UH Series, 1-Func, Low Level Triggered, 1-Bit, True Output, CMOS, PDSO16, 5.30
MM74HC259SJX FAIRCHILD

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 		暂无描述

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