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MM74HC11

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MM74HC11 数据手册

January 1988

MM54HC11/MM74HC11

Triple 3-Input AND Gate

General Description

Features

Typical propagation delay: 12 ns

These AND gates utilize advanced silicon-gate CMOS tech-

nology to achieve operating speeds similar to LS-TTL gates

with the low power consumption of standard CMOS inte-

grated circuits. All gates have buffered outputs, providing

high noise immunity and the ability to drive 10 LS-TTL loads.

The 54HC/74HC logic family is functionally as well as pin-

out compatible with the standard 54LS/74LS logic family.

All inputs are protected from damage due to static dis-

Wide power supply range: 2–6V

Low quiescent current: 20 mA maximum (74HC Series)

Low input current: 1 mA maximum

Fanout of 10 LS-TTL loads

charge by internal diode clamps to V

and ground.

Connection and Logic Diagrams

Dual-In-Line Package

TL/F/5298–1

Top View

Order Number MM54HC11 or MM74HC11

TL/F/5298–2

(1 OF 3 GATES)

1995 National Semiconductor Corporation

TL/F/5298

RRD-B30M105/Printed in U. S. A.

12 3 4 5

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型号	品牌	获取价格	描述	数据表
MM74HC112	NSC	获取价格	Dual J-K Flip-Flop with Preset and Clear
MM74HC112J	TI	获取价格	HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, CE
MM74HC112J	NSC	获取价格	Dual J-K Flip-Flop with Preset and Clear
MM74HC112J/A+	TI	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,HC-CMOS,DIP,16PIN,CERAMIC
MM74HC112M	TI	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,HC-CMOS,SOP,16PIN,PLASTIC
MM74HC112N	NSC	获取价格	IC HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16,
MM74HC112N	TI	获取价格	HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16, PL
MM74HC112N/A+	ROCHESTER	获取价格	J-K Flip-Flop
MM74HC112N/A+	TI	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,HC-CMOS,DIP,16PIN,PLASTIC
MM74HC112N/B+	TI	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,HC-CMOS,DIP,16PIN,PLASTIC