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MM74HC107J PDF预览

MM74HC107J

更新时间: 2024-11-18 05:08:31
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器
页数 文件大小 规格书
6页 130K
描述
MM54HC107/MM74HC107 Dual J-K Flip-Flops with Clear

MM74HC107J 数据手册

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January 1988  
MM54HC107/MM74HC107  
Dual J-K Flip-Flops with Clear  
General Description  
Features  
Y
Typical propagation delay: 16 ns  
These J-K Flip-Flops utilize advanced silicon-gate CMOS  
technology to achieve the high noise immunity and low pow-  
er dissipation of standard CMOS integrated circuits. These  
devices can drive 10 LS-TTL loads.  
Y
Wide operating voltage range: 26V  
Y
Low input current: 1 mA maximum  
Y
Low quiescent current: 40 mA (74HC series)  
Y
These flip-flops are edge sensitive to the clock input and  
change state on the negative going transition of the clock  
pulse. Each one has independent J, K, CLOCK, and CLEAR  
inputs and Q and Q outputs. CLEAR is independent of the  
clock and accomplished by a low level on the input.  
High output drive: 10 LS-TTL loads  
The 54HC/74HC logic family is functionally as well as pin-  
out compatible with the standard 54LS/74LS logic family.  
All inputs are protected from damage due to static dis-  
charge by internal diode clamps to V  
and ground.  
CC  
Connection Diagram  
Truth Table  
Dual-In-Line Package  
Inputs  
Outputs  
CLR  
CLK  
J
K
Q
Q
L
X
X
L
X
L
L
Q0  
H
H
Q0  
L
H
H
H
H
H
v
v
v
v
H
H
L
L
H
H
X
L
H
H
X
TOGGLE  
Q0 Q0  
TL/F/5304–1  
Order Number MM54HC107 or MM74HC107  
Logic Diagram  
TL/F/5304–3  
TL/F/5304–2  
C
1995 National Semiconductor Corporation  
TL/F/5304  
RRD-B30M105/Printed in U. S. A.  

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