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MM74HC04MTCX-F40 PDF预览

MM74HC04MTCX-F40

更新时间: 2024-11-30 14:53:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
9页 329K
描述
Inverter, CMOS, PDSO14

MM74HC04MTCX-F40 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:TSSOP, TSSOP14,.25Reach Compliance Code:compliant
风险等级:5.84JESD-30 代码:R-PDSO-G14
JESD-609代码:e4负载电容(CL):50 pF
逻辑集成电路类型:INVERTER最大I(ol):0.004 A
湿度敏感等级:1端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
电源:2/6 VProp。Delay @ Nom-Sup:24 ns
认证状态:Not Qualified施密特触发器:NO
子类别:Gates表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
Base Number Matches:1

MM74HC04MTCX-F40 数据手册

 浏览型号MM74HC04MTCX-F40的Datasheet PDF文件第2页浏览型号MM74HC04MTCX-F40的Datasheet PDF文件第3页浏览型号MM74HC04MTCX-F40的Datasheet PDF文件第4页浏览型号MM74HC04MTCX-F40的Datasheet PDF文件第5页浏览型号MM74HC04MTCX-F40的Datasheet PDF文件第6页浏览型号MM74HC04MTCX-F40的Datasheet PDF文件第7页 
February 2008  
MM74HC04  
Hex Inverter  
Features  
General Description  
Typical propagation delay: 8ns  
Fan out of 10 LS-TTL loads  
The MM74HC04 inverters utilize advanced silicon-gate  
CMOS technology to achieve operating speeds similar to  
LS-TTL gates with the low power consumption of stan-  
dard CMOS integrated circuits.  
Quiescent power consumption: 10µW maximum at  
room temperature  
The MM74HC04 is a triple buffered inverter. It has high  
noise immunity and the ability to drive 10 LS-TTL loads.  
The 74HC logic family is functionally as well as pin-out  
compatible with the standard 74LS logic family. All inputs  
are protected from damage due to static discharge by  
Low input current: 1µA maximum  
internal diode clamps to V and ground.  
CC  
Ordering Information  
Package  
Order Number Number  
Package Description  
MM74HC04M  
MM74HC04SJ  
MM74HC04MTC  
MM74HC04N  
M14A  
M14D  
MTC14  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.  
All packages are lead free per JEDEC: J-STD-020B standard.  
Connection Diagram  
Logic Diagram  
Pin Assignments for DIP, SOIC, SOP and TSSOP  
1 of 6 Inverters  
Top View  
©1983 Fairchild Semiconductor Corporation  
MM74HC04 Rev. 1.3.0  
www.fairchildsemi.com  

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