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MM74HC04NX PDF预览

MM74HC04NX

更新时间: 2024-09-14 21:53:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
7页 84K
描述
Hex Inverter

MM74HC04NX 数据手册

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September 1983  
Revised January 2005  
MM74HC04  
Hex Inverter  
General Description  
Features  
The MM74HC04 inverters utilize advanced silicon-gate  
CMOS technology to achieve operating speeds similar to  
LS-TTL gates with the low power consumption of standard  
CMOS integrated circuits.  
Typical propagation delay: 8 ns  
Fan out of 10 LS-TTL loads  
Quiescent power consumption: 10 µW maximum at  
room temperature  
The MM74HC04 is a triple buffered inverter. It has high  
noise immunity and the ability to drive 10 LS-TTL loads.  
The 74HC logic family is functionally as well as pin-out  
compatible with the standard 74LS logic family. All inputs  
are protected from damage due to static discharge by inter-  
nal diode clamps to VCC and ground.  
Low input current: 1 µA maximum  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
MM74HC04M  
M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
MM74HC04M_NL  
MM74HC04SJ  
MM74HC04MTC  
MM74HC04MTC_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
MM74HC04N  
N14A  
N14A  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
MM74HC04N_NL  
Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Connection Diagram  
Logic Diagram  
Pin Assignments for DIP, SOIC, SOP and TSSOP  
1 of 6 Inverters  
Top View  
© 2005 Fairchild Semiconductor Corporation  
DS005069  
www.fairchildsemi.com  

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