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MM54HC137 PDF预览

MM54HC137

更新时间: 2024-11-20 22:46:11
品牌 Logo 应用领域
美国国家半导体 - NSC 解码器锁存器
页数 文件大小 规格书
6页 125K
描述
3-to-8 Line Decoder With Address Latches (Inverted Output)

MM54HC137 数据手册

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November 1995  
MM54HC137/MM74HC137 3-to-8 Line  
Decoder With Address Latches  
(Inverted Output)  
General Description  
This device utilizes advanced silicon-gate CMOS technolo-  
gy, to implement a three-to-eight line decoder with latches  
on the three address inputs. When GL goes from low to  
high, the address present at the select inputs (A, B and C) is  
stored in the latches. As long as GL remains high no ad-  
dress changes will be recognized. Output enable controls,  
G1 and G2, control the state of the outputs independently of  
the select or latch-enable inputs. All of the outputs are high  
unless G1 is high and G2 is low. The HC137 is ideally suited  
for the implementation of glitch-free decoders in stored-ad-  
dress applications in bus oriented systems.  
The 54HC/74HC logic family is speed, function and pin-out  
compatible with the standard 54LS/74LS logic family. All  
inputs are protected from damage due to static discharge by  
diodes to V  
and ground.  
CC  
Features  
Y
Typical propagation delay: 20 ns  
Y
Y
Y
Wide supply range: 26V  
Latched inputs for easy interfacing.  
Fanout of 10 LS-TTL loads.  
Connection and Functional Block Diagrams  
Dual-In-Line Package  
TL/F/5310–1  
Order Number MM54HC137  
or MM74HC137  
TL/F/5310–2  
C
1995 National Semiconductor Corporation  
TL/F/5310  
RRD-B30M115/Printed in U. S. A.  

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