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MM54HC148

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MM54HC148 数据手册

February 1988

MM54HC148/MM74HC148

8-3 Line Priority Encoder

General Description

This priority encoder utilizes advanced silicon-gate CMOS

technology. It has the high noise immunity and low power

consumption typical of CMOS circuits, as well as the speeds

and output drive similar to LB-TTL.

All inputs are protected from damage due to static dis-

and ground.

charge by internal diode clamps to V

Features

This priority encoder accepts 8 input request lines 0–7 and

outputs 3 lines A0–A2. The priority encoding ensures that

only the highest order data line is encoded. Cascading cir-

cuitry (enable input EI and enable output EO) has been pro-

vided to allow octal expansion without the need for external

circuitry. All data inputs and outputs are active at the low

logic level.

Typical propagation delay: 13 ns

Wide supply voltage range: 2V–6V

Connection Diagram

Dual-In-Line Package

TL/F/9390–1

Order Number MM54HC148 or MM74HC148

Truth Table

Inputs

Outputs

A2 A1 A0 GS EO

Low, X irrelevant

High, L

1995 National Semiconductor Corporation

TL/F/9390

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6

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