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MM54HC155

更新时间： 2024-11-25 04:39:35
品牌 Logo 应用领域
美国国家半导体 - NSC 解复用器
页数 文件大小 规格书
4页 100K
描述
Dual 2 - To - 4 Line Decoder-Demultiplexers

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中文翻译

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MM54HC155 数据手册

 浏览型号MM54HC155的Datasheet PDF文件第2页浏览型号MM54HC155的Datasheet PDF文件第3页浏览型号MM54HC155的Datasheet PDF文件第4页 
January 1988  
MM54HC155/MM74HC155 Dual 2-To-4  
Line Decoder/Demultiplexers  
General Description  
The device is capable of driving 10 low power Schottky TTL  
equivalent loads.  
The MM54HC155/MM74HC155 is a high speed silicon-gate  
CMOS decoder/demultiplexer. It utilizes advanced silicon-  
gate CMOS technology and features dual 1-line-to-4-line  
demultiplexers with independent strobes and common bina-  
ry-address inputs. When both sections are enabled by the  
strobes, the common address inputs sequentially select and  
route associated input data to the appropriate output of  
each section. The individual strobes permit activating or in-  
hibiting each of the 4-bit sections as desired. Data applied  
to input C1 is inverted at its outputs and data applied to C2  
is non-inverted at its outputs. The inverter following the C1  
data input permits use as a 3-to-8-line decoder, or 1-to-8-  
line demultiplexer, without gating.  
The MM54HC155/MM74HC155 is functionally and pin  
equivalent to the 54LS155/74LS155 with the advantage of  
reduced power consumption.  
Features  
Y
Applications  
Dual 2-to-4-line decoder  
Dual 1-to-4-line demultiplexer  
3-to-8-line decoder  
1-to-8-line demultiplexer  
Y
Typical propagation delay: 22 ns  
Y
Low quiescent current: 80 mA maximum  
(74HC series)  
All inputs to the decoder are protected from damage due to  
and Ground.  
electrostatic discharge by diodes to  
V
CC  
Y
Wide operating range: 2V–6V  
Connect and Logic Diagram  
Truth Tables  
2-to-4-Line Decoder  
or 1-Line to 4-line Demultiplexer  
Inputs  
Strobe  
G1  
Outputs  
Select  
Data  
C1  
B
A
1Y0  
1Y1  
1Y2  
1Y3  
X
L
L
H
H
X
X
L
H
L
H
X
H
L
L
L
L
X
X
H
H
H
H
L
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
L
H
H
H
Inputs  
Strobe  
G2  
Outputs  
Select  
Data  
C2  
B
A
2Y0  
2Y1  
2Y2  
2Y3  
X
L
L
H
H
X
X
L
H
L
H
X
H
L
L
L
L
X
X
L
L
L
L
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
L
H
H
TL/F/8364–1  
Order Number MM54HC155 or  
MM74HC155  
H
3-Line-to-8-Line Decoder  
or 1-Line-to-8-Line Demultiplexer  
Inputs  
Outputs  
Strobe  
Or Data  
Select  
(0) (1) (2) (3) (4) (5) (6) (7)  
2Y0 2Y1 2Y2 2Y3 1Y0 1Y1 1Y2 1Y3  
IC B A  
IG  
X
L
L
L
L
H
H
H
H
X X  
L
L H  
H L  
H H  
H
L
L
L
L
L
L
L
L
H
L
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
L
L
L H  
H L  
H H  
H
H
H
e
IC  
inputs C1 and C2 connected together  
e
IG inputs G1 and G2 connected together  
e
low level X don’t care  
e
e
H
high level L  
C
1995 National Semiconductor Corporation  
TL/F/8364  
RRD-B30M105/Printed in U. S. A.  
1234

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